Memory refresh method and apparatus
First Claim
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1. In an integrated circuit having rows of memory cells selectable through a row address, a method of selectively refreshing the rows comprising:
- monitoring row address activity to identify which bits of the row address change state at least once during a memory access operation; and
skipping refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation.
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Abstract
An integrated circuit includes one or more memory array segments configured to store information and a refresh controller. Each memory array segment has a plurality of memory cells arranged in rows selectable through a row address. The refresh controller is configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation.
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Citations
25 Claims
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1. In an integrated circuit having rows of memory cells selectable through a row address, a method of selectively refreshing the rows comprising:
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monitoring row address activity to identify which bits of the row address change state at least once during a memory access operation; and skipping refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit, comprising:
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one or more memory array segments configured to store information, each memory array segment having a plurality of memory cells arranged in rows selectable through a row address; and a refresh controller configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. In an integrated circuit having rows of memory cells selectable through a row address, a method of selectively refreshing the rows comprising:
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identifying one or more bits of the row address which do not change state at least once when the integrated circuit is active; skipping refresh of the rows selectable through the identified row address bits; and determining a refresh clock frequency based on how many row address bits are identified. - View Dependent Claims (16, 17, 18)
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19. An integrated circuit, comprising:
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one or more memory array segments configured to store information, each memory array segment having a plurality of memory cells arranged in rows selectable through a row address; and a refresh controller configured to identify one or more bits of the row address which do not change state at least once when the integrated circuit is active, to skip refresh of the rows selectable through the identified row address bits, and to determine a refresh clock frequency based on how many row address bits are identified. - View Dependent Claims (20, 21, 22)
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23. A system, comprising:
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a controller; one or more memory array segments coupled to the controller and configured to store information, each memory array segment having a plurality of memory cells arranged in rows selectable through a row address; and a refresh controller configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation. - View Dependent Claims (24, 25)
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Specification