Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects

• US 7,552,040 B2
• Filed: 02/13/2003
• Issued: 06/23/2009
• Est. Priority Date: 02/13/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Soreff, Jeffrey Paul, Rosser, Thomas Edward, Dorfman, Barry Lee
• Primary Examiner(s): Shah; Kamini S
• Assistant Examiner(s): Gebresilassie; Kibrom K
• Application Number:
  US10/366,439
• Publication Number:
  US 20040162716A1
• Time in Patent Office: 2,322 Days
• Field of Search: 703/14, 703/15, 703/19, 703/2, 703/13, 703/21, 703/22, 716/1, 716/6, 714/741, 714/742
• US Class Current: 703/13
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.

Claims

1. A method for determining coefficients for a logical circuit block model, comprising:

determining a value of a simulated gate current conducted from a logical circuit block output into a gate of a loading circuit transistor during simulations of performance of said logical circuit block;

simulating a current-dependent current source conducted from said logical circuit block output to a return path during said simulations of performance;

setting a magnitude of the current-dependent current source to a value computed according to a model from the determined value of the simulated gate current, wherein the magnitude of the current-dependent current source is set in proportion to the determined value of the simulated gate current according to a proportion;

repeatedly calculating a logical circuit block performance value while varying the proportion in order to simulate different sizes of the loading circuit transistor;

computing said coefficients from a result of the calculating, wherein the coefficients are coefficients that relate the logical circuit block performance value to a capacitance of said gate of said loading circuit transistor from a result of said calculating and said varying; and

storing said coefficients in a computer memory.

2. The method of claim 1, further comprising second simulating an independently variable shunt capacitance connected from said logical circuit block output to a return path, whereby effects of a static loading capacitance on said logical circuit block performance value is simulated.

3. A method for modeling, in a computer system, the behavior of a logical circuit block, the method comprising:

first calculating in said computer system a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block and a static load capacitance value, wherein said first mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value;

second calculating in said computer system a delay time of said logical circuit block as a second mathematical function of said transistor gate capacitance and said static load capacitance value, wherein said second mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value; and

displaying by said computer system, a result of at least one of said first and second calculating, and wherein coefficients of said first and second mathematical function with respect to said transistor gate capacitance are determined in advance of said first calculating and said second calculating by determining a value of a simulated gate current conducted from a logical circuit block output into a gate of a loading circuit transistor of said one or more logical circuit inputs during simulations of said transition time and said delay time of said logical circuit block, and further simulating a current-dependent current source conducted from said output of said logical circuit block to a return path during said simulations of said transition time and said delay time, setting a magnitude of the current-dependent current source to a value computed according to a model from the determined value of the simulated gate current, varying a proportion of the model relating the magnitude of the current-dependent current source to the determined value of the simulated gate current to simulate different sizes of the loading circuit transistor while determining said transition time and said delay time, and calculating said coefficients from a result of said varying and said determining said transition time and said delay time.

4. A workstation computer system including a memory for storing program instructions and data, and a processor for executing said program instructions, and wherein said program instructions comprise program instructions for:

first calculating a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block and a static load capacitance value, wherein said first mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value;

second calculating delay time of said logical circuit block as a second mathematical function of said transistor gate capacitance and said static load capacitance value, wherein said second mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value; and

displaying a result of at least one of said first and second calculating, and wherein said program instructions further comprise additional program instructions for calculating coefficients of said first and second mathematical function with respect to said transistor gate capacitance by determining a value of a simulated gate current conducted from a logical circuit block output into a gate of a loading circuit transistor of said one or more logical circuit inputs during simulations of said transition time and said delay time of said logical circuit block, and further simulating a current-dependent current source conducted from said output of said logical circuit block to a return path during said simulations of said transition time and said delay time, setting a magnitude of the current-dependent current source to a value computed according to a model from the determined value of the simulated gate current, varying a proportion of the model relating the magnitude of the current-dependent current source to the determined value of the simulated gate current to simulate different sizes of the loading circuit transistor while determining said transition time and said delay time, and calculating said coefficients from a result of said varying and said determining said transition time and said delay time.

5. A computer program product comprising a computer-readable storage medium encoding program instructions and data for execution on a general-purpose computer system, wherein said program instructions comprise program instructions for:

first calculating a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block and a static load capacitance value, wherein said first mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value;

second calculating delay time of said logical circuit block as a second mathematical function of said transistor gate capacitance and said static load capacitance value, wherein said second mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value;

displaying a result of at least one of said first and second calculating;

calculating coefficients of said first and second mathematical function with respect to said transistor gate capacitance by determining a value of a simulated gate current conducted from a logical circuit block output into a gate of a loading circuit transistor of said one or more logical circuit inputs during simulations of said transition time and said delay time of said logical circuit block;

simulating a current-dependent current source conducted from said output of said logical circuit block to a return path during said simulations of said transition time and said delay time;

setting a magnitude of the current-dependent current source to a value computed from the determined value of the simulated gate current according to a proportion;

varying the proportion to simulate different sizes of the loading circuit transistor while determining said transition time and said delay time; and

calculating said coefficients from a result of said varying and said determining said transition time and said delay time.