Single-chip multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage
First Claim
1. A single-chip flash device comprising:
- an interface to a host bus that connects to a host;
a bus transceiver for detecting and processing commands sent over the host bus;
a buffer for storing data sent over the host bus;
an internal bus coupled to the buffer;
a random-access memory (RAM) for storing instructions for execution;
the RAM coupled to the internal bus,a central processing unit (CPU) coupled to the internal bus, the CPU accessing and executing instructions in the RAM;
a flash-memory controller, coupled to the internal bus, for generating flash-control signals and for buffering commands, addresses, and data to a flash bus;
a direct-memory access (DMA) engine, coupled to the internal bus, for transferring data over the internal bus;
flash mass storage blocks, coupled to the flash-memory controller, for storing non-volatile data for the host, the data in the flash mass storage blocks being block-addressable and controlled by the flash-control signals;
a flash programming engine, activated by a reset, for initially programming the DMA engine to transfer an initial program of instructions from the flash mass storage blocks to the RAM before the CPU begins execution of instructions after the reset; and
wherein the flash-memory controller is coupled to the flash mass storage blocks that are block-addressable;
the flash bus having parallel data lines for transferring data from the flash-memory controller to the flash mass storage blocks, the flash bus also carrying a command to the flash mass storage blocks over the parallel data lines and also carrying a flash address over the parallel data lines;
wherein a block of data in the flash mass storage blocks is addressable by the flash-memory controller sending the command and a physical address over the parallel data lines, the command and the physical address being used to transfer the block of data over the parallel data lines as a plurality of data words transferred in a plurality of bus cycles,wherein the flash mass storage blocks comprise a plurality of multi-level-logic (MLC) memory cells.
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Accused Products
Abstract
A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.
3 Citations
11 Claims
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1. A single-chip flash device comprising:
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an interface to a host bus that connects to a host; a bus transceiver for detecting and processing commands sent over the host bus; a buffer for storing data sent over the host bus; an internal bus coupled to the buffer; a random-access memory (RAM) for storing instructions for execution;
the RAM coupled to the internal bus,a central processing unit (CPU) coupled to the internal bus, the CPU accessing and executing instructions in the RAM; a flash-memory controller, coupled to the internal bus, for generating flash-control signals and for buffering commands, addresses, and data to a flash bus; a direct-memory access (DMA) engine, coupled to the internal bus, for transferring data over the internal bus; flash mass storage blocks, coupled to the flash-memory controller, for storing non-volatile data for the host, the data in the flash mass storage blocks being block-addressable and controlled by the flash-control signals; a flash programming engine, activated by a reset, for initially programming the DMA engine to transfer an initial program of instructions from the flash mass storage blocks to the RAM before the CPU begins execution of instructions after the reset; and wherein the flash-memory controller is coupled to the flash mass storage blocks that are block-addressable; the flash bus having parallel data lines for transferring data from the flash-memory controller to the flash mass storage blocks, the flash bus also carrying a command to the flash mass storage blocks over the parallel data lines and also carrying a flash address over the parallel data lines; wherein a block of data in the flash mass storage blocks is addressable by the flash-memory controller sending the command and a physical address over the parallel data lines, the command and the physical address being used to transfer the block of data over the parallel data lines as a plurality of data words transferred in a plurality of bus cycles, wherein the flash mass storage blocks comprise a plurality of multi-level-logic (MLC) memory cells. - View Dependent Claims (2)
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3. A dual-mode flash drive comprising:
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a dual-mode switch that connects to a host over a host bus, and connects to downstream devices over a plurality of buses; a flash microcontroller having a processor; a main memory coupled to the processor for storing instructions for execution by the processor; an interface for switching to one of a plurality of buses; a plurality of single-chip flash devices, coupled to the dual-mode switch as the downstream devices, each single-chip flash device comprising; a flash-memory controller; a plurality of flash mass storage blocks that are block-accessible by the processor through the flash-memory controller; a direct-memory access (DMA) engine for directly transferring data and instructions over an internal bus among the interface, the main memory, the processor, and the flash-memory controller; a flash programming engine for initially programming the DMA engine to read an initial program from a first page of the plurality of flash mass storage blocks and write the initial program to the main memory for execution by the processor. - View Dependent Claims (4)
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5. A single-chip flash device comprising:
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a Multi-Media Card/Secure Digital (MMC/SD) interface that connects to a host over a MMC/SD host bus; a MMC/SD-flash microcontroller having a processor for executing instructions; a main memory coupled to the processor for storing instructions for execution by the processor; a flash-memory controller; a flash mass storage block that is block-accessible by the processor through the flash-memory controller; wherein the flash mass storage block comprises a plurality of multi-level-logic (MLC) memory cells; a direct-memory access (DMA) engine for directly transferring data and instructions over an internal bus among the MMC/SD interface, the main memory, the processor, and the flash-memory controller; a flash programming engine for initially programming the DMA engine to read an initial program from a first page of the flash mass storage block and write the initial program to the main memory for execution by the processor. - View Dependent Claims (6, 7)
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8. A single-module flash device comprising:
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a Multi-Media Card/Secure Digital (MMC/SD) interface that connects to a host over a MMC/SD host bus; a MMC/SD-flash microcontroller having a processor for executing instructions; a main memory coupled to the processor for storing instructions for execution by the processor; a flash-memory controller; a plurality of flash mass storage blocks that are block-accessible by the processor through the flash-memory controller; wherein the plurality of flash mass storage blocks comprise a plurality of multi-level-logic (MLC) memory cells; a direct-memory access (DMA) engine for directly transferring data and instructions over an internal bus among the MMC/SD interface, the main memory, the processor, and the flash-memory controller; a flash programming engine for initially programming the DMA engine to read an initial program from a first page of the plurality of flash mass storage blocks and write the initial program to the main memory for execution by the processor. - View Dependent Claims (9, 10, 11)
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Specification