Automated wear leveling in non-volatile storage systems
First Claim
1. A memory system comprising:
- a plurality of units of erasable and re-programmable non-volatile memory cells having contiguous physical addresses organized into zones with address boundaries therebetween and wherein a distinct range of logical addresses are mapped into each of the zones; and
a memory controller that reassigns the boundary addresses to delete at least one unit from each of the zones and to add said at least one unit to an adjacent zone without changing the number of units in the individual zones, the memory controller subsequently accessing the zones for programming data to or reading data from the reassigned memory cell units therein according to logical addresses of the data, and the memory controller repetitively reassigning the boundary addresses and accessing the zones at least until the plurality of memory cell units have all been moved from their zones to adjacent zones, thereby to spread out usage of the units accessed through the logical addresses;
wherein reassigning the boundary addresses includes deleting a number of units from each of the zones less than ten percent of the units within the zone and adding said number of units to an adjacent zone.
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Abstract
Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. Included is a method for performing wear leveling in a memory system that includes a first zone, which has a first memory element that includes contents, and a second zone includes identifying the first memory element and associating the contents of the first memory element with the second zone while disassociating the contents of the first memory element from the first zone. In one embodiment, associating the contents of the first memory element with the second involves moving contents of a second memory element into a third memory element, then copying the contents of the first memory element into the second memory element.
131 Citations
9 Claims
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1. A memory system comprising:
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a plurality of units of erasable and re-programmable non-volatile memory cells having contiguous physical addresses organized into zones with address boundaries therebetween and wherein a distinct range of logical addresses are mapped into each of the zones; and a memory controller that reassigns the boundary addresses to delete at least one unit from each of the zones and to add said at least one unit to an adjacent zone without changing the number of units in the individual zones, the memory controller subsequently accessing the zones for programming data to or reading data from the reassigned memory cell units therein according to logical addresses of the data, and the memory controller repetitively reassigning the boundary addresses and accessing the zones at least until the plurality of memory cell units have all been moved from their zones to adjacent zones, thereby to spread out usage of the units accessed through the logical addresses; wherein reassigning the boundary addresses includes deleting a number of units from each of the zones less than ten percent of the units within the zone and adding said number of units to an adjacent zone. - View Dependent Claims (2, 3, 4, 5)
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6. A memory system comprising:
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a memory array having a plurality of zones individually including a plurality of units of re-programmable non-volatile memory cells that are erasable together, wherein a distinct range of logical addresses received by the memory system are mapped into the individual zones; and circuitry that receives a logical address within the distinct logical address range of one of the zones, and converts the received logical address into a physical address of at least one of the plurality of memory cell erase units within said one zone that tends to even out a number of usage cycles of erasing and re-programming the erase units within said one zone; wherein the converted address represented less than ten percent of the distinct logical address range of said one of the zones. - View Dependent Claims (7, 8, 9)
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Specification