Performance of a cache by detecting cache lines that have been reused
First Claim
Patent Images
1. A system, comprising:
- a processor, wherein said processor has a cache associated with it;
a system memory for storing data of said processor;
a bus system coupling said processor to said system memory;
wherein said cache comprises;
a data array comprising a plurality of congruence classes, wherein each of said congruence classes groups a plurality of cache lines;
a tag array comprising a plurality of tags, wherein each of said plurality of tags is associated with one of said plurality of cache lines, wherein each of said plurality tags comprises a bit used to indicate whether its associated cache line has been reused;
logic for receiving a request of an address of data;
logic determining if said requested data is located in said cache;
logic for setting said bit in said tag associated with a cache line in a congruence class to a second state if said requested data is located within said cache line of said cache; and
logic for resetting said bit for one of said plurality of cache lines in said congruence class if a number of cache lines in said congruence class identified as being reused exceeds a threshold.
2 Assignments
0 Petitions
Accused Products
Abstract
A method and system for improving the performance of a cache. The cache may include an array of tag entries where each tag entry includes an additional bit (“reused bit”) used to indicate whether its associated cache line has been reused, i.e., has been requested or referenced by the processor. By tracking whether a cache line has been reused, data (cache line) that may not be reused may be replaced with the new incoming cache line prior to replacing data (cache line) that may be reused. By replacing data in the cache memory that might not be reused prior to replacing data that might be reused, the cache hit may be improved thereby improving performance.
10 Citations
8 Claims
-
1. A system, comprising:
-
a processor, wherein said processor has a cache associated with it; a system memory for storing data of said processor; a bus system coupling said processor to said system memory; wherein said cache comprises; a data array comprising a plurality of congruence classes, wherein each of said congruence classes groups a plurality of cache lines; a tag array comprising a plurality of tags, wherein each of said plurality of tags is associated with one of said plurality of cache lines, wherein each of said plurality tags comprises a bit used to indicate whether its associated cache line has been reused; logic for receiving a request of an address of data; logic determining if said requested data is located in said cache; logic for setting said bit in said tag associated with a cache line in a congruence class to a second state if said requested data is located within said cache line of said cache; and logic for resetting said bit for one of said plurality of cache lines in said congruence class if a number of cache lines in said congruence class identified as being reused exceeds a threshold. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
Specification