Method for maintaining atomicity of instruction sequence to access a number of cache lines during proactive synchronization within a computer system
First Claim
1. A method comprising:
- a processor that implements an x86 architecture requesting exclusive access to a given memory resource, wherein the requesting includes executing a critical section of code having one or more memory reference instructions, wherein the one or more memory reference instructions comprise mov instructions, each having an x86 LOCK instruction prefix followed by an acquire instruction, wherein during a specification phase, each mov instruction having the x86 LOCK instruction prefix specifies a corresponding memory address associated with the given memory resource;
in response to execution of each mov instruction having the x86 LOCK prefix, storing the corresponding memory address within a processor buffer;
in response to execution of the acquire instruction;
sending each memory address stored within the processor buffer to be compared; and
comparing each memory address specified in the critical section of code to each address of a plurality of sets of addresses, wherein each address of the plurality of sets of addresses corresponds to a respective memory resource to which a requestor has been granted exclusive access; and
in response to any memory address of the critical section of code matching any address of a plurality of sets of addresses, causing the acquire instruction to fail; and
inhibiting modifying data corresponding to any memory address specified by the one or more mov instructions having the x86 LOCK instruction prefix in the critical section of code.
1 Assignment
0 Petitions
Accused Products
Abstract
A method for maintaining atomicity of a sequence of instructions includes a processor requesting exclusive access to a given memory resource. The request may include executing a critical section of code having memory reference instructions each including a LOCK prefix, and the memory reference instructions may be followed by an ACQUIRE instruction. The method also includes comparing each memory address of the critical section of code to each address of sets of addresses in response to execution of the ACQUIRE instruction. Each address of the sets of addresses corresponds to a respective memory resource to which a requester has exclusive access. In response to any memory address of the critical section of code matching any address of the sets of addresses, the method includes causing the ACQUIRE instruction to fail, and inhibiting modifying data corresponding to any memory address in an atomic phase of the critical section of code.
36 Citations
20 Claims
-
1. A method comprising:
-
a processor that implements an x86 architecture requesting exclusive access to a given memory resource, wherein the requesting includes executing a critical section of code having one or more memory reference instructions, wherein the one or more memory reference instructions comprise mov instructions, each having an x86 LOCK instruction prefix followed by an acquire instruction, wherein during a specification phase, each mov instruction having the x86 LOCK instruction prefix specifies a corresponding memory address associated with the given memory resource; in response to execution of each mov instruction having the x86 LOCK prefix, storing the corresponding memory address within a processor buffer; in response to execution of the acquire instruction; sending each memory address stored within the processor buffer to be compared; and comparing each memory address specified in the critical section of code to each address of a plurality of sets of addresses, wherein each address of the plurality of sets of addresses corresponds to a respective memory resource to which a requestor has been granted exclusive access; and in response to any memory address of the critical section of code matching any address of a plurality of sets of addresses, causing the acquire instruction to fail; and inhibiting modifying data corresponding to any memory address specified by the one or more mov instructions having the x86 LOCK instruction prefix in the critical section of code. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A computer system comprising:
-
a plurality of processors that implement an x86 architecture, and coupled together and to one or more memories, wherein each of the processors is configured to execute instructions to request exclusive access to a given memory resource, wherein the request includes a specification phase of a critical section of code having one or more memory reference instructions, wherein the one or more memory reference instructions comprise mov instructions, each having an x86 LOCK instruction prefix, followed by an acquire instruction, wherein each mov instruction having the x86 LOCK instruction prefix specifies a corresponding memory address associated with the given memory resource; and wherein in response to execution of each mov instruction having the x86 LOCK prefix, the processor is configured to store the corresponding memory address within a buffer of the requesting processor; wherein in response to execution of the acquire instruction the processor is configured to send each memory address stored within the buffer to be compared; an arbitration unit coupled to the plurality of processors and configured to compare each memory address of the specification phase the critical section of code to each address of a plurality of sets of addresses in response to execution of the acquire instruction, wherein each address of the plurality of sets of addresses corresponds to a respective memory resource to which a requestor has been granted exclusive access; wherein in response to any memory address of the critical section of code matching any address of a plurality of sets of addresses, each of the processors is configured to; cause the acquire instruction to fail; and inhibit modifying data corresponding to any memory address specified by the one or more mov instructions having the x86 LOCK instruction prefix in the critical section of code. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification