Method of determining plasma ion density, wafer voltage, etch rate and wafer current from applied bias voltage and current

• US 7,553,679 B2
• Filed: 08/23/2006
• Issued: 06/30/2009
• Est. Priority Date: 05/16/2003
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Hoffman, Daniel J.
• Primary Examiner(s): Le; Thoa X
• Assistant Examiner(s): Lee; Kyoung
• Application Number:
  US11/508,346
• Publication Number:
  US 20060278608A1
• Time in Patent Office: 1,042 Days
• Field of Search: 438/10, 438/712, 438/715, 438/729, 156/345.25, 156/345.28, 156/345.44, 216/61
• US Class Current: 438/14
• CPC Class Codes: H01J 37/32174 Circuits specially adapted for controlling the RF discharge
• CPC Class Codes: H01J 37/32935 Monitoring and controlling tubes by information coming from the object and/or discharge

Abstract

Plasma parameters such as plasma ion density, wafer voltage, etch rate and wafer current in the chamber are determined from external measurements on the applied RF bias electrical parameters such as voltage and current. The method includes sensing RF parameters corresponding to an input impedance, an input current and an input voltage at the input of the impedance match element to a transmission line coupled between the bias generator and the wafer pedestal. The method continues by computing a junction admittance of a junction between the transmission line and the electrode within the wafer pedestal from the input impedance, input current and input voltage and from parameters of the transmission line. The method further includes providing shunt electrical quantities of a shunt capacitance between the electrode and a ground plane, and providing load electrical quantities of a load capacitance between the electrode and a wafer on the pedestal. The method further includes computing at least one of the plasma parameters from the junction admittance, the shunt electrical quantities, the load electrical quantities and a frequency of RF bias power applied to the electrode.

Claims

1. In a plasma reactor chamber having a wafer support pedestal for supporting a wafer inside the reactor, said pedestal having an insulated electrode beneath the wafer and a transmission line coupling said electrode to a bias impedance match element for an RF bias generator, a method of determining plasma ion density, wafer voltage, etch rate and wafer current in said chamber, said method comprising:

sensing RF parameters corresponding to an input impedance, an input current and an input voltage at the input of said impedance match element to said transmission line;

computing a junction admittance of a junction between said transmission line and the electrode within the wafer pedestal from said input impedance, input current and input voltage and from parameters of the transmission line;

providing shunt electrical quantities of a shunt capacitance between the electrode and a ground plane;

providing load electrical quantities of a load capacitance between the electrode and a wafer on the pedestal;

computing at least one of said etch rate, plasma ion density and wafer voltage and wafer current from said junction admittance, said shunt electrical quantities, said load electrical quantities and a frequency of RF bias power applied to said electrode.

2. The method of claim 1 wherein said parameters of said transmission line processor comprise a length of said transmission line, a characteristic impedance of said transmission line and a complex loss factor of said transmission line.

3. The method of claim 2 further comprising computing said shunt electrical quantities from the size of an electrode-to-ground gap length, an area of said wafer, an electrode-to-ground dielectric constant and an electrode-to-ground conductive loss component.

4. The method of claim 3 further comprising computing said load electrical quantities from an electrode-to-wafer gap length, an area of the wafer, an electrode-to-wafer dielectric constant and an electrode-to-wafer conductive loss component.

5. The method of claim 4 wherein the step of computing said etch rate and plasma ion density comprises:

first computing said wafer voltage V_wafer and an imaginary part of a plasma admittance comprising a plasma susceptance b, and computing said ion density and etch rate from said wafer voltage and said plasma susceptance.

6. The method of claim 5 further comprising computing said plasma admittance by the following steps:

computing a wafer impedance from said junction admittance, said shunt electrical quantities and said load electrical quantities;

computing said plasma admittance as a reciprocal of said wafer impedance.

7. The method of claim 6 wherein the etch rate is computed as the product of the squares of said plasma susceptance and said wafer voltage.

8. The method of claim 6 wherein the ion density is computed as kb²(V_wafer)^3/2 where k is a predetermined constant.

9. The method of claim 6 wherein the ion density is computed as kb²(V_wafer)² where k is a predetermined constant.