Structure and method for forming a minimum pitch trench-gate FET with heavy body region
First Claim
1. A method of forming a field effect transistor, comprising:
- forming openings in a masking layer extending over a surface of a silicon region;
forming a trench in the silicon region through each opening in the masking layer;
forming a layer of silicon along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening;
removing the masking layer to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region; and
forming a contact layer to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon.
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Accused Products
Abstract
A field effect transistor is formed as follows. Openings are formed in a masking layer extending over a surface of a silicon region. A trench is formed in the silicon region through each opening in the masking layer. A layer of silicon is formed along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening. The masking layer is removed to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region. A contact layer is formed to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon.
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Citations
32 Claims
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1. A method of forming a field effect transistor, comprising:
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forming openings in a masking layer extending over a surface of a silicon region; forming a trench in the silicon region through each opening in the masking layer; forming a layer of silicon along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening; removing the masking layer to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region; and forming a contact layer to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of forming a field effect transistor, comprising:
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forming openings in a masking layer extending over a surface of a silicon region; forming a trench in the silicon region through each opening in the masking layer; forming a layer of silicon along sidewalls and bottom of each trench and along masking layer sidewalls which define the openings in the masking layer; and removing the masking layer to thereby form contact openings over the surface of the silicon region for receiving a contact layer, the contact openings being defined by exposed sidewalls of the layer of silicon. - View Dependent Claims (9, 10, 11, 12)
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13. A method of forming a field effect transistor, comprising:
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forming trenches in a silicon region using a masking layer, the trenches extending from a surface of the silicon region to a predetermined depth in the silicon region; removing portions of the masking layer to expose surface areas of the silicon region adjacent each trench; forming a layer of silicon along sidewalls and bottom of each trench, the layer of silicon extending out of each trench and over the exposed surface areas of the silicon region adjacent each trench, the layer of silicon abutting sidewalls of the masking layer remaining after the removing step; and removing the remaining masking layer to thereby form contact openings over the surface of the silicon region, the contact openings being defined by exposed sidewalls of the layer of silicon. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A method of forming a field effect transistor, comprising:
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forming a pair of trenches in a silicon region; forming a layer of silicon extending along sidewalls and bottom of each trench, the layer of silicon further extending out of each trench but being discontinuous over a surface of the silicon region so as to form a contact opening over the surface of the silicon region between the pair of trenches, the contact opening being formed without removing a portion of the layer of silicon; and through the contact opening, forming a heavy body region in the silicon region between the pair of trenches. - View Dependent Claims (20, 21)
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22. A field effect transistor comprising:
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a pair of trenches in a silicon region; and a layer of silicon extending along the sidewalls and bottom of each trench, the layer of silicon extending out of each trench but being discontinuous over a surface of the silicon region so as to form a contact opening over the surface of the silicon region between the pair of trenches, wherein the contact opening is self-aligned relative to the trenches. - View Dependent Claims (23, 24, 25, 26, 27)
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28. A field effect transistor comprising:
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a plurality of trenches in a silicon region; a layer of silicon lining sidewalls and bottom of each trench, the layer of silicon extending out of each trench but being discontinuous over a surface of the silicon region so as to form a contact opening over the surface of the silicon region between adjacent trenches, wherein the contact opening is self-aligned relative to the trenches; a gate dielectric layer lining sidewalls and bottom of the layer of silicon in each trench; a gate electrode over the gate dielectric in each trench; and source regions of a first conductivity type extending into the layer of silicon. - View Dependent Claims (29, 30, 31, 32)
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Specification