Process for producing semiconductor integrated circuit device

• US 7,553,756 B2
• Filed: 11/13/2006
• Issued: 06/30/2009
• Est. Priority Date: 11/16/2005
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Aoki, Hideo, Hayashi, Hiroyuki, Oshima, Takayuki
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): Kim; Su C
• Application Number:
  US11/598,084
• Publication Number:
  US 20070111508A1
• Time in Patent Office: 960 Days
• Field of Search: 438/319, 438411-413, 438421-422, 438/619, 438/622, 438/623, 438/584, 438/597, 438/618, 438/624, 257/522, 257/E21.573
• US Class Current: 438/622
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 2221/1026 the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An object of the present invention is to prevent formation of a badly situated via metal in a Damascene wiring portion in multiple layers having an air-gap structure. In the present invention, a via is completely separated from an air-gap 45 by forming an interlayer insulating film 44 having the air-gap 45 between adjacent Damascene wiring portions after forming a sacrifice film pillar 42 from a selectively removable insulating film in a formation region of a connection hole. The present invention can provide multiple-layered buried wiring in which a high reliable via connection and a reduced parasitic capacitance due to the air-gap are achieved.

Claims

1. A process for producing a semiconductor integrated circuit device, comprising the steps of:

(a) providing a first insulating film over a semiconductor substrate;

(b) providing a plurality of wiring grooves in the first insulating film;

(c) forming a first conductive film on the first insulating film including respective insides of the plurality of the wiring grooves;

(d) removing the first conductive film lying outside the plurality of the wiring grooves to form a wiring line composed of the first conductive film in respective insides of the plurality of the wiring grooves;

(e) forming a second insulating film from material different than that of the first insulating film on the first insulating film and the wiring line;

(f) etching the second insulating film by using a mask covering a formation region of a connection hole to be formed in a later step for exposing the upper surface of the wiring line, to form a sacrifice film pillar composed of the second insulating film in the formation region of the connection hole;

(g) selectively removing the first insulating film in a region not covered with the sacrifice film pillar to leave behind the first insulating film under the sacrifice film pillar;

(h) forming a third insulating film from material different than that of the second insulating film on the wiring line and the sacrifice film pillar, while leaving behind an air-gap in a space region between the wiring line portions on which the first insulating film was removed;

(i) removing the third insulating film on the sacrifice film pillar to expose the upper surface of the sacrifice film pillar;

(j) removing the sacrifice film pillar to form the connection hole for exposing the upper surface of the wiring line; and

(k) forming a second conductive film inside the connection hole.

2. The process for producing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film and the third insulating film are formed from the same material.

3. The process for producing a semiconductor integrated circuit device according to claim 2, wherein the first insulating film and the third insulating film are an inorganic insulating film, and the second insulating film is an organic insulating film.

4. The process for producing a semiconductor integrated circuit device according to claim 3, wherein the first insulating film and the third insulating film are an FSG film, and the second insulating film is a SiLK film.

5. The process for producing a semiconductor integrated circuit device according to claim 1, further including a step of forming a SIC film on the wiring line and the sacrifice film pillar between the steps (g) and (h), wherein the third insulating film is a porous SiOC film.

6. The process for producing a semiconductor integrated circuit device according to claim 5, wherein the first insulating film is an FSG film, and the second insulating film is a SiLK film.

7. The process for producing a semiconductor integrated circuit device according to claim 1, wherein the first conductive film is formed from at least any one of metals including Al, Cu, W, Ag and Au.

8. The process for producing a semiconductor integrated circuit device according to claim 1, wherein the second conductive film is formed from at least any one of metals including Al, Cu, W, Ag and Au.

9. The process for producing a semiconductor integrated circuit device according to claim 1, further including a step of forming a metal cap film on the wiring line between the steps (d) and (e), wherein the metal cap film is formed from at least any one of metals and metallic compounds including Co, W, Ni, Cr and Au.

10. The process for producing a semiconductor integrated circuit device according to claim 1, wherein the formation of the third insulating film in the step (h) is performed using a low coverage formation condition during an initial formation step, and after the formation of the air-gap, using a high coverage formation condition.

11. A process for producing a semiconductor integrated circuit device, comprising the steps of:

(a) providing a first insulating film over a semiconductor substrate;

(b) removing a part of the first insulating film to form a plurality of first wiring grooves for a first Damascene wiring portion to be formed in a later step;

(c) forming a first conductive film on the first insulating film including respective insides of the plurality of the first wiring grooves;

(d) removing the first conductive film lying outside the plurality of the first wiring grooves to form the first Damascene wiring portion composed of the first conductive film in respective insides of the plurality of the first wiring grooves;

(e) forming a second insulating film from material different than that of the first insulating film on the first insulating film and the first Damascene wiring portion;

(f) etching the second insulating film using a mask covering a formation region of a plurality of connection holes to be formed in a later step for a via portion of a second Damascene wiring portion to form a plurality of sacrifice film pillars composed of the second insulating film in the formation region of the plurality of the connection holes;

(g) selectively removing the first insulating film in a region not covered with the sacrifice film pillars to leave behind the first insulating film under the sacrifice film pillars;

(h) forming a third insulating film from material different than that of the second insulating film on the wiring portion and the sacrifice film pillars, while leaving behind an air-gap in a space region between the wiring portions on which the first insulating film was removed;

(i) removing the third insulating film on the sacrifice film pillars to expose the upper surface of the plurality of the sacrifice film pillars;

(j) removing a part of the third insulating film and the top of the plurality of the sacrifice film pillars to form a plurality of second wiring grooves for wiring of the second Damascene wiring portion to be formed in a later step;

(k) removing the bottom of the plurality of the sacrifice film pillars to form the plurality of the connection holes;

(l) forming a second conductive film on the third insulating film including respective insides of the plurality of the second wiring grooves and the plurality of the connection holes; and

(m) removing the second conductive film lying outside the plurality of the second wiring grooves and the plurality of the connection holes to form the second Damascene wiring portion composed of the second conductive film in respective insides of the plurality of the second wiring grooves and the plurality of the connection holes.

12. The process for producing a semiconductor integrated circuit device according to claim 11, wherein the first insulating film and the third insulating film are formed from the same material.

13. The process for producing a semiconductor integrated circuit device according to claim 12, wherein the first insulating film and the third insulating film are an inorganic insulating film, and the second insulating film is an organic insulating film.

14. The process for producing a semiconductor integrated circuit device according to claim 13, wherein the first insulating film and the third insulating film are an FSG film, and the second insulating film is a SiLK film.

15. The process for producing a semiconductor integrated circuit device according to claim 11, wherein the first conductive film and the second conductive film are formed from at least any one of metals including Al, Cu, W, Ag and Au.

16. The process for producing a semiconductor integrated circuit device according to claim 11, further including a step of forming a metal cap film on the first Damascene wiring portion and the second Damascene wiring portion between the steps (d) and (g) and after the step (m), wherein the metal cap film is formed from at least any one of metals and metallic compounds including Co, W, Ni, Cr and Au.

17. The process for producing a semiconductor integrated circuit device according to claim 11, wherein the formation of the third insulating film in the step (h) is performed using a low coverage formation condition during an initial formation step, and after the formation of the air-gap, using a high coverage formation condition.

18. The process for producing a semiconductor integrated circuit device according to claim 11, wherein the formation of the plurality of the second wiring grooves in the step (i) is performed by removing a part of the third insulating film after removing the top of the plurality of the sacrifice film pillars.

19. The process for producing a semiconductor integrated circuit device according to claim 11, wherein the formation of the plurality of the second wiring grooves in the step (i) is performed by using a hard mask composed of a fourth insulating film.

20. The process for producing a semiconductor integrated circuit device according to claim 19, wherein the fourth insulating film is a SiN film.