Scanning imager employing multiple chips with staggered pixels
First Claim
1. A CMOS imaging system comprisingan array of pixels arranged into rows and columns on an imaging area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series;
- an array of microlenses disposed on the imaging area, each microlens covering a plurality of said pixels;
each said column having a column amplifier FET having a source electrode and a drain electrode;
at least one pair of conductors associated with the first series of columns, with the source and drain electrodes of the column amplifier FETs of the first series of columns being respectively connected thereto;
at least one pair of conductors associated with the second series of columns, with the source and drain electrodes of the column amplifier FETs of the second series of columns being respectively connected thereto;
first and second output amplifiers each including an additional FET and a feedback path coupled to the respective pair of conductors of the respective series of columns; and
image control circuitry coupled to the pixels of said imager;
wherein said image control circuitry includes means for applying, for each said plurality of pixels, different integration times to the different respective ones of the plurality of pixels under the same microlens.
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Abstract
A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk. An array of microlenses is situated with each microlens covering a plurality of the pixels. The different pixels under each microlens can be aligned along a diagonal. The different pixels under the same microlens can have different integration times, to increase the dynamic range of the imager(s).
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Citations
15 Claims
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1. A CMOS imaging system comprising
an array of pixels arranged into rows and columns on an imaging area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series; -
an array of microlenses disposed on the imaging area, each microlens covering a plurality of said pixels; each said column having a column amplifier FET having a source electrode and a drain electrode; at least one pair of conductors associated with the first series of columns, with the source and drain electrodes of the column amplifier FETs of the first series of columns being respectively connected thereto; at least one pair of conductors associated with the second series of columns, with the source and drain electrodes of the column amplifier FETs of the second series of columns being respectively connected thereto; first and second output amplifiers each including an additional FET and a feedback path coupled to the respective pair of conductors of the respective series of columns; and image control circuitry coupled to the pixels of said imager;
wherein said image control circuitry includes means for applying, for each said plurality of pixels, different integration times to the different respective ones of the plurality of pixels under the same microlens. - View Dependent Claims (2, 3)
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4. A CMOS imaging system comprising
an array of pixels arranged into rows and columns on an imaging area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series; -
an array of microlenses disposed on the imaging area, each microlens covering a plurality of said pixels; each said column having a column amplifier FET having a source electrode and a drain electrode; at least one pair of conductors associated with the first series of columns, with the source and drain electrodes of the column amplifier FETs of the first series of columns being respectively connected thereto; at least one pair of conductors associated with the second series of columns, with the source and drain electrodes of the column amplifier FETs of the second series of columns being respectively connected thereto; first and second output amplifiers each including an additional FET and a feedback path coupled to the respective pair of conductors of the respective series of columns; and image control circuitry coupled to the pixels of said imager; and wherein die pixels of each said plurality of pixels are arranged in pairs of pixel regions arranged diagonally on two sides of a pixel control region such that the pairs of pixel regions each extend diagonally defining diagonal zones between successive pairs of pixel regions of that series, wherein the pixels of the other pluralities of pixels are situated within said diagonal zones, and wherein the microlenses are arranged over the pixels within said diagonal zones. - View Dependent Claims (5, 6)
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7. A CMOS imaging system comprising
an array of pixels arranged into rows and columns on an imagine area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series; -
an array of microlenses disposed on the imagine area, each microlens covering a plurality of said pixels; each said column having a column amplifier FET having a source electrode and a drain electrode; at least one pair of conductors associated with the first series of columns. with the source and drain electrodes of the column amplifier FETs of the first series of columns being respectively connected thereto; at least one pair of conductors associated with the second series of columns, with the source and drain electrodes of the column amplifier FETs of the second series of columns being respectively connected thereto; first and second output amplifiers each including an additional FET and a feedback path coupled to the respective pair of conductors of the respective series of columns; image control circuitry coupled to the pixels of said imager; wherein corresponding pixels of the first and second series of columns are diagonally offset from one another; and wherein the pixels are arranged in pairs of pixel regions arranged diagonally on two sides of a pixel control region such that the pairs of pixel regions each extend diagonally defining diagonal zones between successive pairs of pixel regions of that series, and wherein the pixels of the other series of columns of pixels are situated within said diagonal zones. - View Dependent Claims (8, 9, 10)
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11. A CMOS imaging system comprising
an array of pixels arranged into rows and columns on an imaging area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series, and each said pixel having a photosensitive pixel area; -
an array of microlenses disposed on the imaging area, each microlens covering a plurality of said pixels; each said column having a column amplifier; and image control circuitry coupled to the pixels of said imager;
wherein said image control circuitry includes means for applying, for each said plurality of pixels covered by a respective one of said microlenses. different integration times to the different pixels under the same microlens. - View Dependent Claims (12, 13)
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14. A video camera comprising:
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lens for focusing an image of an object; a photo sensor placed at an image plane of said lens; and output circuitry coupled to said photo sensor for generating a video output signal; wherein said photo sensor includes; an array of pixels arranged into rows and columns on an imaging area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series; each said column having a column amplifier FET having a source electrode and a drain electrode; at least one pair of conductors associated with the first series of columns, with the source and drain electrodes of the column amplifier FETs of the first series of columns being respectively connected thereto; at least one pair of conductors associated with the second series of columns, with the source and drain electrodes of the column amplifier FETs of the second series of columns being respectively connected thereto; first and second output amplifiers each including an additional PET and a feedback path coupled to the respective pair of conductors of the respective series of columns; and image control circuitry coupled to the pixels of said imager; wherein corresponding pixels of the first and second series of columns are diagonally offset from one another; wherein the pixels are arranged in pairs of pixel regions arranged diagonally on two sides of a pixel control region such that the pairs of pixel regions each extend diagonally defining diagonal zones between successive pairs of pixel regions of that series; wherein the pixels of the other series of columns of pixels are situated within said diagonal zones; and further comprising an array of microlenses disposed on said imaging area, wherein each of the microlenses thereof is disposed over a plurality of the pixels thereof. - View Dependent Claims (15)
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Specification