HfAlO3 films for gate dielectrics
First Claim
1. A transistor comprising:
- a body region between a first and a second source/drain region;
a dielectric film disposed on the body region between the first and second source/drain regions, the dielectric film containing a layer of HfAlO3, the layer of HfAlO3 having a thickness, the thickness being essentially equal to a minimum number of monolayers of HfAlO3 to provide a bulk band gap of the HfAlO3; and
a gate coupled to and contacting the dielectric film.
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Accused Products
Abstract
A dielectric film containing HfAlO3 and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is formed by atomic layer deposition employing a hafnium sequence and an aluminum sequence. The hafnium sequence uses HfCl4 and water vapor. The aluminum sequence uses either trimethylaluminium, Al(CH3)3, or DMEAA, an adduct of alane (AlH3) and dimethylehtylamine [N(CH3)2(C2H5)], with distilled water vapor. These gate dielectrics containing a HfAlO3 film are thermodynamically stable such that the HfAlO3 film will have minimal reactions with a silicon substrate or other structures during processing.
679 Citations
29 Claims
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1. A transistor comprising:
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a body region between a first and a second source/drain region; a dielectric film disposed on the body region between the first and second source/drain regions, the dielectric film containing a layer of HfAlO3, the layer of HfAlO3 having a thickness, the thickness being essentially equal to a minimum number of monolayers of HfAlO3 to provide a bulk band gap of the HfAlO3; and a gate coupled to and contacting the dielectric film. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 27)
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9. A transistor comprising:
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a body region between a first and a second source/drain region; a film disposed on the body region between the first and second source/drain regions, the film containing a layer of HfAlO3 and a layer of HfO2 such that the layer of HfAlO3 has a thickness, the thickness being essentially equal to a minimum number of monolayers of HfAlO3 to provide a bulk band gap of the HfAlO3; and a gate coupled to and contacting the film; the film formed by atomic layer deposition including; pulsing a hafnium containing precursor into a reaction chamber containing a substrate; pulsing a first oxygen containing precursor into the reaction chamber; pulsing an aluminum containing precursor into a reaction chamber; and pulsing a second oxygen containing precursor into the reaction chamber. - View Dependent Claims (10, 11, 12)
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13. A memory having a memory array comprising:
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a number of access transistors, each access transistor including a gate coupled to and contacting a film, the film containing a layer of HfAlO3 and a layer of HfO2 such that the layer of HfAlO3 a thickness, the thickness being essentially equal to a minimum number of monolayers of HfAlO3 to provide a bulk band gap of the HfAlO3, the film formed on a body region between a first and a second source/drain regions; a number of word lines coupled to a number of the gates of the number of access transistors; a number of source lines coupled to a number of the first source/drain regions of the number of access transistors; and a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors; the film formed by atomic layer deposition including; pulsing a hafnium containing source gas into a reaction chamber containing a substrate; pulsing an aluminum containing source gas into the reaction chamber. - View Dependent Claims (14, 15, 16)
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17. A memory having a memory array comprising:
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a number of access transistors, each access transistor including a gate coupled to and contacting a film, the film containing a layer of HfAlO3, the layer of HfAlO3 having a thickness, the thickness being essentially equal to a minimum number of monolayers of HfAlO3 to provide a bulk band gap of the HfAlO3, the film disposed on a body region between a first and a second source/drain regions; a number of word lines coupled to a number of the gates of the number of access transistors; a number of source lines coupled to a number of the first source/drain regions of the number of access transistors; and a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors. - View Dependent Claims (18, 19, 28)
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20. An electronic system comprising:
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a processor; a memory, the memory having an array including; a number of access transistors, each access transistor having a gate coupled to and contacting a film, the film containing a layer of HfAlO3 and a layer of HfO2 such that the layer of HfAlO3 has a thickness, the thickness being essentially equal to a minimum number of monolayers of HfAlO3 to provide a bulk band gap of the HfAlO3, the film formed on a body region between a first and a second source/drain regions; a number of word lines coupled to a number of the gates of the number of access transistors; a number of source lines coupled to a number of the first source/drain regions of the number of access transistors; a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors; and a system bus that couples the processor to the memory array; the HfAlO3 formed by atomic layer deposition including; pulsing a hafnium containing source gas into a reaction chamber containing a substrate; and pulsing an aluminum containing source gas into a reaction chamber. - View Dependent Claims (21, 22, 23)
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24. An electronic system comprising:
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a processor; and a memory, the memory having an array including; a number of access transistors, each access transistor having a gate coupled to and contacting a film, the film containing a layer of HfAlO3, the layer of HfAlO3 having a thickness, the thickness being essentially equal to a minimum number of monolayers of HfAlO3 to provide a bulk band gap of the HfAlO3, the film formed on a body region between a first and a second source/drain regions; a number of word lines coupled to a number of the gates of the number of access transistors; a number of source lines coupled to a number of the first source/drain regions of the number of access transistors; a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors; and a system bus that couples the processor to the memory array. - View Dependent Claims (25, 26, 29)
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Specification