Flip chip and wire bond semiconductor package

• US 7,554,185 B2
• Filed: 10/31/2005
• Issued: 06/30/2009
• Est. Priority Date: 12/14/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Foong, Chee Seng, Lo, Wai Yew, Liu, Jin- Mei, Song, Fu- Bin, Ismail, Aminuddin, Wang, Jian- Hong, Liau, Bee Hoon, Yao, Jin- Zhong
• Primary Examiner(s): Tran, Long K
• Application Number:
  US11/718,396
• Publication Number:
  US 20080111248A1
• Time in Patent Office: 1,338 Days
• Field of Search: 257/778, 257/686, 257/774, 257/E25.013, 257/782, 257/784
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

A semiconductor package and method of forming the package, including a substrate having an opening formed therein. Contact pads are formed about a periphery of the opening on a first side of the substrate and a second opposing side of the substrate. A flip chip die is mounted to the substrate, having an active side mounted on a first side of the substrate and in electrical communication with at least some of the contact pads formed on the first side of the substrate. At least one wire bond die is mounted through the opening, with a non-active side mounted on the active side of the flip chip die. The wire bond die is in electrical communication with at least some of the plurality of contact pads formed on the second opposing side of the substrate.

Claims

1. A semiconductor package comprising:

a substrate, including an opening formed therein;

a plurality of contact pads formed about a periphery of the opening on a first side of the substrate and a second opposing side of the substrate;

a flip chip die, having an active side mounted on the first side of said substrate in electrical communication with at least some of the contact pads formed on the first side of the substrate;

a plurality of wire bond die, each having a perimeter size of less than the dimension of the opening, and having a non-active side attached to the active side of the flip chip die, wherein the plurality of wire bond die in electrical communication with at least some of the plurality of contact pads formed on the second opposed side of the substrate;

first wires electrically connecting the plurality of wire bond die to respective ones of the contact pads on the second side of the substrate; and

second wires electrically connecting the plurality of wire bond die directly to the flip chip die.

2. The semiconductor package as claimed in claim 1, wherein the substrate further includes a ball grid array formed on the second opposed side of the substrate for external electrical connection.

3. The semiconductor package as claimed in claim 1, wherein the flip chip die is mounted to the first side of the substrate using a plurality of solder bumps.

4. The semiconductor package as claimed in claim 1, further including a heat sink attached to an uppermost surface of the flip chip die, wherein the heat sink is in direct contact with said uppermost surface of the flip chip die.

5. A semiconductor package comprising:

a substrate, including an opening formed therein;

a plurality of contact pads formed about a periphery of the opening on a first side of the substrate and a second opposing side of the substrate;

a flip chip die, having an active side mounted on a first side of said substrate in electrical communication with at least some of the contact pads formed on the first side of the substrate; and

a plurality of wire bond die, having a side-by-side mounting dimension of less than the dimension of the opening, the plurality of wire bond die mounted through the opening in a side-by-side formation, and having each non-active side mounted on the active side of the flip chip die, each of the plurality of wire bond die in electrical communication with at least some of the plurality of contact pads formed on the second side of the substrate.

6. The semiconductor package as claimed in claim 5, wherein the substrate further includes a ball grid array formed on the second side of the substrate for external electrical communication.

7. The semiconductor package as claimed in claim 5, wherein the flip chip die is mounted to the first side of the substrate using a plurality of solder bumps.

8. The semiconductor package as claimed in claim 5, wherein each of the plurality of wire bond die is electrically coupled to the second side of the substrate with a plurality of wires via a wire bonding process.

9. The semiconductor die package as claimed in claim 5, further including a heat sink formed on an uppermost surface of the flip chip die.