Digital dead-time controller for pulse width modulators
First Claim
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1. A digital dead-time controller comprising:
- a controller receiving a system clock and each of a plurality of phase-shifted versions of the system clock employed by a digital pulse width modulator, the controller further comprising;
first logic causing a duration of an output transistor control signal controlling a first output transistor driving an output node to be increased by a first selected multiple of phase-divisions of the system clock; and
second logic causing a leading edge of the output transistor control signal to be advanced relative to the system clock by a second selected multiple of phase-divisions of the system clock.
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Abstract
Dead-time gaps are inserted into one of two output transistor control signals from a digital pulse width modulator by controlling the leading and trailing edges using the same phase-division and dithering signals employed by the digital pulse width modulator. Adders add the phase select signals from the digital pulse width modulator and the dithering signal to the leading and trailing edge control signals, with the output employed by multiplexers as select controls in selecting a phase of from the phase-shifted versions of the system clock with which to clock latches controlling the leading and trailing edges.
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13 Claims
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1. A digital dead-time controller comprising:
a controller receiving a system clock and each of a plurality of phase-shifted versions of the system clock employed by a digital pulse width modulator, the controller further comprising; first logic causing a duration of an output transistor control signal controlling a first output transistor driving an output node to be increased by a first selected multiple of phase-divisions of the system clock; and second logic causing a leading edge of the output transistor control signal to be advanced relative to the system clock by a second selected multiple of phase-divisions of the system clock. - View Dependent Claims (2, 3)
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4. A digital dead-time controller comprising:
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a controller receiving a system clock and each of a plurality of phase-shifted versions of the system clock employed by a digital pulse width modulator, the controller further comprising; first logic causing a duration of an output transistor control signal controlling a first output transistor driving an output node to be increased by a first selected multiple of phase-divisions of the system clock; and second logic causing a leading edge of the output transistor control signal to be advanced relative to the system clock by a second selected multiple of phase-divisions of the system clock; a first multiplexer receiving an output of the first logic as select controls, an output of the first multiplexer clocking a first latch controlling timing of a trailing edge of the output transistor control signal; and a second multiplexer receiving an output of the second logic as select controls, an output of the second multiplexer clocking a second latch controlling timing of a leading edge of the output transistor control signal. - View Dependent Claims (5, 6, 7)
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8. A digital dead-time control method comprising:
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receiving a system clock and each of a plurality of phase-shifted versions of the system clock employed by a digital pulse width modulator; increasing a duration of an output transistor control signal controlling a first output transistor driving an output node by a first selected multiple of phase-divisions of the system clock; and advancing a leading edge of the output transistor control signal relative to the system clock by a second selected multiple of phase-divisions of the system clock. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification