Multi-mode power amplifier with low gain variation over temperature

• US 7,554,407 B2
• Filed: 03/07/2007
• Issued: 06/30/2009
• Est. Priority Date: 03/07/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Turpel, Jeffrey R., Hau, Gary
• Primary Examiner(s): Shingleton; Michael B
• Application Number:
  US11/683,128
• Publication Number:
  US 20080218270A1
• Time in Patent Office: 846 Days
• Field of Search: 330/289, 330/124.R, 330/124.D, 330/278, 455/73
• US Class Current: 330/289
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/30 Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in differential amplifiers H03F3/45479
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/447 the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/7231 the gated amplifier being switched on or off by putting into cascade or not, by choosing between amplifiers by one or more switch(es)
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

A multi-mode RF amplifier is described having at least a higher and a lower power path coupling an input to an output. At a pre-selected output power level, the higher power path is enabled while the lower power path is disabled when more output power is required. The process is reversed when less power is needed. The present invention matches the power gain variation over temperature characteristic of each path such that, especially at the cross over point, the gain delta (the difference in power gain between the two paths) has minimal variation over temperature. Such power gain characteristic is required for meeting the test requirements, specifically the inner loop power control, for third generation (3G) cellular handsets.

Claims

1. A multi-mode amplifier defining an input and an output, the multi-mode amplifier comprising:

a first higher power amplifier transferring the input to the output, the first higher power amplifier comprising a higher power transistor arranged to provide an increased power gain when its DC collector current is increased and a reduced power gain with rising temperature;

a first bias circuit configured to provide a first base current to the higher power transistor, wherein the first base current increases when temperature increases, wherein the rate of increase in the first base current is higher than the rate of decrease in DC current gain of the higher power transistor with rising temperature and, hence, increases the DC collector current of the higher power transistor at higher temperatures, but wherein the result is a decrease in power gain with rising temperature;

a second lower power amplifier in parallel with the first higher power amplifier, the second lower power amplifier comprising a lower power transistor arranged to provide a reduced power gain when its DC collector current is decreased and a reduced power gain with rising temperature; and

a second bias circuit configured to provide a second base current to the lower power transistor, wherein, although the second base current increases with rising temperature, the rate of increase in the second base current is lower than the rate of decrease in DC current gain of the lower power transistor with rising temperature and, hence, decreases the DC collector current of the lower power transistor at higher temperatures, wherein the result is a decrease in power gain with rising temperature, and wherein the magnitude of decrease in power gain of the higher power amplifier approximately matches the magnitude of decrease in power gain of the lower power amplifier when the temperature rises.

2. The multi-mode amplifier of claim 1 wherein the first bias circuit includes a first reference current that mirrors the DC collector current of the higher power transistor and the second bias circuit includes a second reference current that mirrors the DC collector current of the lower power transistor.

3. The multi-mode amplifier of claim 2 wherein the second reference current is at least four times lower than the first reference current, and wherein the rate of increase in the second reference current available for mirroring with rising temperature is lower than the first reference current.

4. The multi-mode amplifier of claim 3 further comprising an emitter follower transistor that diverts some of the second reference current wherein it is not mirrored in the lower power transistor DC collector current.

5. The multi-mode amplifier of claim 1 wherein the first bias circuit includes:

a first bias transistor with its base coupled to the base of the higher power transistor and the emitters coupled together to ground such that the first bias transistor forms a current mirror with the higher power transistor;

a first resistor coupled from the collector of the first bias transistor to a power supply, wherein the base emitter junctions voltage drops of the first bias and the higher power transistor decrease with increasing temperature, wherein the base emitter junction voltages drop of the first bias circuit and the higher power transistor decrease with increasing temperature, wherein the first reference current through the first resistor increases with increasing temperature, wherein the first base current of the higher power transistor increases with temperature, wherein the rate of increase in the first base current is higher than the rate of decrease in DC current gain of the higher power transistor with rising temperature and, hence, increases the DC collector current of the higher power transistor at higher temperatures; and

a second bias transistor with its collector coupled to a power supply, its base coupled to the collector of the first bias transistor, and its emitter coupled to the common bases of the higher power and first bias transistors, wherein the base currents for both the higher power and first bias transistors are supplied by the emitter of the second bias transistor.

6. The multi-mode amplifier of claim 1 wherein the second bias circuit includes:

a third bias transistor with its emitter coupled to the base of the lower power transistor;

a fourth bias transistor with its collector coupled to a power supply, its base connected to the base of the third bias transistor and its emitter connected to a second resistor to ground;

a fifth bias transistor with its collector connected to the bases of the third and the fourth bias transistors, its base is connected to the emitter of the fourth bias transistor and its emitter is connected to ground;

a third resistor coupled from the collector of the fifth bias transistor to a power supply;

wherein the second and third resistors are selected such that a second reference current through the third resistor is a mirror of the DC collector current of the lower power transistor; and

wherein the base emitter junction voltages drop of the third, fourth, and fifth bias transistors and the lower power transistor decrease with increasing temperature, wherein the second reference current through the third resistor increases with increasing temperature, wherein the second base current of the lower power transistor increases with temperature, wherein the rate of increase in the second base current is lower than the rate of decrease in DC current gain of the lower power transistor with rising temperature and, hence, decreases the DC collector current of the lower power transistor at higher temperatures.

7. A method for amplifying a signal traveling through a multi-mode amplifier from an input to an output, the method comprising the steps of:

first transferring the input to the output via a higher power transistor, wherein when temperature increases the power gain of the higher power transistor decreases;

increasing the DC collector current of the higher power transistor as the temperature rises, partially compensating for the decrease in power gain with rising temperature;

second transferring, in parallel with the first transferring, the input to the output via a lower power transistor, wherein when the temperature increases the power gain of the lower power transistor decreases; and

decreasing the DC collector current of the lower power transistor as the temperature rises, further decreasing the power gain of the lower power transistor, wherein the magnitude of decrease in power gain of the higher power transistors (approximately) matches the magnitude of decrease in power gain of the lower power transistor.

8. The method of claim 7 wherein the step of increasing the DC collector current of the higher power transistor includes a step of first mirroring the DC collector current of the higher power transistor and increasing the first reference current that mirrors the higher power transistor'"'"'s DC collector current.

9. The method of claim 7 further wherein the step of decreasing the DC collector current of the lower power transistor includes a step of second mirroring the DC collector current of the lower power transistor and increasing the second reference current that mirrors the lower power transistor'"'"'s DC collector current, and wherein the second reference current is at least four time lower than the first reference current.

10. A multi-mode amplifier comprising:

means for first transferring the input to the output via a higher power transistor, wherein the power gain of the higher power transistor decreases with rising temperature;

means for increasing the power gain of the higher power transistor by increasing the DC collector current of the higher power transistor when the temperature rises, partially compensating for the decrease in power gain with rising temperature;

means for second transferring, in parallel with the first transferring, the input to the output via a lower power transistor; and

means for decreasing the power gain of the lower power transistor by decreasing the DC collector current of the lower power transistor with rising temperature, wherein the magnitude of decrease in power gain of the higher power transistor (approximately) matches the magnitude of decrease in power gain of the lower power transistor with rising temperature.

11. The multi-mode amplifier of claim 10 wherein the means for increasing the DC collector current of the higher power transistor includes:

means for mirroring the DC collector current of the higher power transistor; and

means for increasing a first reference current.

12. The multi-mode amplifier of claim 10 wherein the means for decreasing the DC collector current of the lower power transistor includes:

means for mirroring the DC collector current of the lower power transistor; and

means for increasing a second reference current.

13. The multi-mode amplifier of claim 10 further wherein the means for mirroring includes:

means for creating a voltage drop across a first resistor with the first reference current, wherein the voltage drop increases with temperature that increases the first reference current and thereby increases the DC collector current of the higher power transistor.

14. A multi-mode amplifier defining an input and an output, the amplifier comprising:

a higher power path comprising a higher power transistor and a first bias circuit providing and controlling DC collector current of the higher power transistor;

a lower power path comprising a lower power transistor and a second bias circuit providing and controlling DC collector current of the lower power transistor; and

wherein the first bias circuit provides that the DC collector current of the higher power transistor increases with temperature, and wherein the second bias circuit provides that the DC collector current of the lower power transistor decreases with temperature, wherein the higher power path exhibits a reduced power gain variation with temperature, and the lower power path exhibits an increased power gain variation with temperature that matches the power gain variation with temperature of the higher power transistor.

15. The multi-mode amplifier of claim 14 wherein the first bias circuit has a mirror circuit that controls the DC collector current of the higher power transistor, and the second bias circuit has a mirror circuit that controls the DC collector current of the lower power transistor.

16. The multi-mode amplifier of claim 14 wherein the higher and lower power transistors comprise Heterojunction Bipolar Transistors (HBTs).

17. The multi-mode amplifier of claim 14 wherein the first bias circuit provides a first base current to the higher power transistor that increases with rising temperature, and the second bias circuit provides a second base current to the lower power transistor that increases with rising temperature.

18. A multi-mode power amplifier having an input and an output, the muulti-mode amplifier comprising:

a first higher power amplifier transferring the input to the output, the first higher power amplifier comprising a higher power transistor arranged to provide an increased power gain when its DC collector current is increased and a reduced power gain with rising temperature;

a first reference current arranged in a first bias circuit configured to provide a first base current to the higher power transistor, wherein the DC collector current of the higher power transistor is a mirror of the first reference current, and wherein the DC collector current of the higher power transistor rises at higher temperatures, but wherein the result is a decrease in power gain with rising temperature;

a second lower power amplifier in parallel with the first higher power amplifier, the second lower power amplifier comprising a lower power transistor arranged to provide a reduced power gain when its DC collector current is decreased and a reduced power gain with rising temperature; and

a second reference current arranged in a second bias circuit configured to provide a second base current to the lower power transistor, wherein the DC collector current of the lower power transistor is a mirror of the second reference current, and wherein second reference current is at least four times lower than the first reference current such that the DC collector current of the lower power transistor decreases with rising temperatures, and wherein the result is a decrease in power gain with rising temperature, and wherein the magnitude of decrease in power gain of the higher power amplifier approximately matches the magnitude of decrease in power gain of the lower power amplifier when the temperature rises.