Feedforward sigma-delta ad converter with an optimized built-in filter function

• US 7,554,474 B2
• Filed: 12/04/2006
• Issued: 06/30/2009
• Est. Priority Date: 12/05/2005
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Le Guillou, Yann
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US12/096,210
• Publication Number:
  US 20080309535A1
• Time in Patent Office: 939 Days
• Field of Search: 341/155, 341/144, 341/143, 341/139
• US Class Current: 341/143
• CPC Class Codes: H03M 3/30 Delta-sigma modulation
• CPC Class Codes: H03M 3/368 of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/452 with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input

Abstract

The present invention relates to a receiver apparatus, analog-to-digital converter apparatus, and method of converting an analog input signal into a digital output signal, wherein an additional direct feedforward path is introduced to compensate for peaking of feedforward structures while preserving frequency selectivity of the feedforward topology. In particular, the direct feedforward path (72) is provided with a scaling by a direct feedforward coefficient (ao) greater than zero and less than one. As a result, overshoot or peaking of classical feedforward topologies can be suppressed while providing interferer immunity, anti-aliazing effects and loop stability.

Claims

1. An analog-to-digital converter (ADC) apparatus for converting an analog input into a digital output signal, said ADC apparatus comprising:

feedforward means for processing a derived signal according to a predetermined filtering function to obtain a processed signal;

compensating means for receiving said analog input signal and for generating a compensation signal to be combined with said processed signal to obtain a combined signal;

single-bit or multi-bit quantizer means for converting said combined signal into said digital output signal;

feedback means for generating an analog feedback signal by digital-to-analog converting said digital output signal, and for subtracting said analog feedback signal from said analog input signal to obtain said derived signal; and

anti-aliasing filter means for suppressing alias signals, wherein alias suppression of said anti-aliasing filter means is set by a scaling coefficient less than one and greater than zero,

wherein said compensating means comprise scaling means for scaling said analog input signal by applying said scaling coefficient to generate said compensation signal.

2. The apparatus of claim 1, wherein said compensating means comprise a direct feedforward path.

3. The apparatus of claim 1, wherein said filtering function of said feedforward means has a low-pass characteristic.

4. The apparatus of claim 1, wherein said scaling coefficient is optimized according to the following expression:

$\begin{array}{cc}{a}_0=\left({5.10}^{-2}<br><br>{\mathrm{Ain}}_{\mathrm{rms}}<br><br>\sqrt{2}+0.135\right)<br><br>5<br><br>\frac{{\mathrm{\omega <br><br>}}_1}{\mathrm{mfs}}<br><br>a_1& \end{array}$

wherein Ain_rms denotes the maximum in-band RMS input signal, ω

₁ denotes the characteristic angular frequency of a first order term of said filtering function, a₁ denotes the coefficient of said first order term of said filtering function, and mfs denotes a sampling frequency of said ADC apparatus.

5. The apparatus of claim 1, further comprising at least one of high-pass filter means for filtering said analog feedback signal and low-pass filter means for filtering said derived signal.

6. The apparatus of claim 5, wherein said high-pass filter means and said low-pass filter means have the same cut-off frequency.

7. The apparatus of claim 1, wherein said anti-aliasing filter means comprise a fifth order loop filter.

8. The apparatus of claim 1, wherein said anti-aliasing filter means are based on at least one of an OTA and a gm-C topology.

9. The apparatus of claim 1, wherein said anti-aliasing filter means has a purely resistive or a purely capacitive feedforward coefficient.

10. The apparatus of claim 1, wherein said anti-aliasing filter means is based on a cascaded loop implementation.

11. The apparatus of claim 1, wherein said ADC apparatus is a sigma-delta ADC.

12. The apparatus of claim 1, wherein said ADC apparatus is implemented in discrete or continuous-time topology.

13. A receiver apparatus comprising the ADC apparatus of claim 1.

14. The receiver apparatus of claim 13, wherein said receiver apparatus is a multi-band receiver for combined reception of cellular and other wireless signals.

15. A method of converting an analog input signal into a digital output signal, said method comprising:

generating a feedforward signal by processing a derived signal according to a filtering function;

combining said feedforward signal with a compensation signal generated from said analog input signal to obtain a combined signal;

converting said combined signal into said digital output signal;

generating an analog feedback signal by digital-to-analog converting said digital output signal;

suppressing alias signals of said digital output signal by an anti-aliasing filter using a scaling coefficient less than one and greater than zero; and

subtracting said analog feedback signal from said analog input signal to obtain said derived signal;

wherein said compensation signal is generated by applying said scaling coefficient to said analog input signal.

16. The method of claim 15, wherein said anti-aliasing filter comprises a fifth order loop filter.

17. The method of claim 15, wherein said anti-aliasing filter is based on at least one of an OTA and a gm-C topology.

18. The method of claim 15, wherein said anti-aliasing filter has a purely resistive or a purely capacitive feedforward coefficient.

19. The method of claim 15, wherein said anti-aliasing filter is based on a cascaded loop implementation.

20. An analog-to-digital converter (ADC) apparatus for converting an analog input into a digital output signal, said ADC apparatus comprising:

feedforward means for processing a derived signal according to a predetermined filtering function to obtain a processed signal;

compensating means for receiving said analog input signal and for generating a compensation signal to be combined with said processed signal to obtain a combined signal;

single-bit or multi-bit quantizer means for converting said combined signal into said digital output signal; and

feedback means for generating an analog feedback signal by digital-to-analog converting said digital output signal, and for subtracting said analog feedback signal from said analog input signal to obtain said derived signal;

wherein said compensating means comprise scaling means for scaling said analog input signal by applying a scaling coefficient less than one and greater than zero, to generate said compensation signal, said scaling coefficient optimized according to the following expression;

$\begin{array}{cc}{a}_0=\left({5.10}^{-2}<br><br>{\mathrm{Ain}}_{\mathrm{rms}}<br><br>\sqrt{2}+0.135\right)<br><br>5<br><br>\frac{{\mathrm{\omega <br><br>}}_1}{\mathrm{mfs}}<br><br>a_1& \end{array}$

wherein Aim_rms denotes the maximum in-band RMS input signal, ω

₁ denotes the characteristic angular frequency of a first order term of said filtering function, a₁ denotes the coefficient of said first order term of said filtering function, and mfs denotes a sampling frequency of said ADC apparatus.

21. An analog-to-digital converter (ADC) apparatus for converting an analog input into a digital output signal, said ADC apparatus comprising:

feedforward means for processing a derived signal according to a predetermined filtering function to obtain a processed signal;

compensating means for receiving said analog input signal and for generating a compensation signal to be combined with said processed signal to obtain a combined signal;

single-bit or multi-bit quantizer means for converting said combined signal into said digital output signal;

feedback means for generating an analog feedback signal by digital-to-analog converting said digital output signal, and for subtracting said analog feedback signal from said analog input signal to obtain said derived signal; and

at least one of high-pass filter means for filtering said analog feedback signal and low-pass filter means for filtering said derived signal;

wherein said compensating means comprise scaling means for scaling said analog input signal by applying a scaling coefficient less than one and greater than zero, to generate said compensation signal.

22. The apparatus of claim 21, wherein said high-pass filter means and said low-pass filter means have the same cut-off frequency.

23. A method of converting an analog input signal into a digital output signal, said method comprising:

generating a feedforward signal by processing a derived signal according to a filtering function;

combining said feedforward signal with a compensation signal generated from said analog input signal to obtain a combined signal;

converting said combined signal into said digital output signal;

generating an analog feedback signal by digital-to-analog converting said digital output signal; and

subtracting said analog feedback signal from said analog input signal to obtain said derived signal,

wherein said compensation signal is generated by applying a scaling less than one and greater than zero to said analog input signal, said scaling coefficient optimized according to the following expression;

$\begin{array}{cc}{a}_0=\left({5.10}^{-2}<br><br>{\mathrm{Ain}}_{\mathrm{rms}}<br><br>\sqrt{2}+0.135\right)<br><br>5<br><br>\frac{{\mathrm{\omega <br><br>}}_1}{\mathrm{mfs}}<br><br>a_1& \end{array}$

wherein Ain_rms denotes the maximum in-band RMS input signal, ω

₁ denotes the characteristic angular frequency of a first order term of said filtering function, a₁ denotes the coefficient of said first order term of said filtering function, and mfs denotes a sampling frequency of said ADC apparatus.

24. A method of converting an analog input signal into a digital output signal, said method comprising:

generating a feedforward signal by processing a derived signal according to a filtering function;

combining said feedforward signal with a compensation signal generated from said analog input signal to obtain a combined signal;

converting said combined signal into said digital output signal;

generating an analog feedback signal by digital-to-analog converting said digital output signal;

subtracting said analog feedback signal from said analog input signal to obtain said derived signal; and

performing at least one of filtering said analog feedback signal with a high pass filter and filtering said derived signal with a low-pass filter;

wherein said compensation signal is generated by applying a scaling less than one and greater than zero to said analog input signal.

25. The method of claim 24, wherein said high-pass filter and said low-pass filter have the same cut-off frequency.