Graphics display system with anti-flutter filtering and vertical scaling feature

• US 7,554,553 B2
• Filed: 12/18/2007
• Issued: 06/30/2009
• Est. Priority Date: 11/09/1998
• Status: Expired due to Fees

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Kranawetter, Greg A., Patterson, James T., Xie, Xiaodong
• Primary Examiner(s): Sajous; Wesner
• Application Number:
  US11/959,139
• Publication Number:
  US 20080094506A1
• Time in Patent Office: 560 Days
• Field of Search: 345/581, 345589-592, 345600-606, 345618-619, 345/660, 345/520, 345629-630, 345/522, 345/556, 345545-547, 348/441, 348/450, 348/453, 348/477, 348469-470, 348495-496, 348500-502, 348518-521, 348/533, 348/557, 348537-539, 382/162, 382/167
• US Class Current: 345/589
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 : using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440263 : by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/04 : Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0122 : the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Claims

1. A processor for communications, comprising:

at least one interface operable to receive input image data and provide output image data for presentation on an electronic screen; and

at least one module operable to perform at least one post-processing function on the input image data to obtain the output image data,

wherein the processor is operable to receive the input image data from at least one other module, and provide the output image data to a buffer to store the output image data prior to presentation on the electronic screen,

wherein the input image data is in a YCrCb format with a luminance component and red and blue chrominance components, and

wherein the at least one module is operable to perform upsampling of the input image data for the red and blue chrominance components.

2. The processor of claim 1, wherein the at least one module is operable to perform flipping, texture mapping, and shading of the input image data.

3. The processor of claim 1, wherein the at least one module is operable to perform conversion from a first video format used for the input image data to a second video format used for the output image data.

4. The processor of claim 1, wherein the at least one module is operable to process the input image data to scale up or down an image in size.

5. The processor of claim 1, wherein the at least one module is operable to combine input image data for first and second images to obtain the output image data for a composite image.

6. The processor of claim 5, wherein the first image is a video image or a graphics image and the second image is text.

7. The processor of claim 1, wherein the at least one module is operable to alpha-blend two images to obtain a composite image.

8. The processor of claim 7, wherein the at least one module is operable to alpha-blend the composite image with a video image to obtain the output image data.

9. The processor of claim 1, wherein the at least one module is operable to perform transparency to superimpose a first image over a second image.

10. The processor of claim 1, wherein the at least one module is operable to perform alpha-blending of a first image and a second image.

11. The processor of claim 10, wherein an alpha value is selected for chroma keying.

12. The processor of claim 1, further comprising:

a programmable instruction processor operable to receive instructions and direct the at least one module to process the input image data in accordance with the received instructions.

13. The processor of claim 1, further comprising:

a memory to store the output image data until the buffer is ready to accept the output image data.

14. The processor of claim 1, wherein the at least one interface unit is operable to provide the output image data in an output format selected from among a plurality of possible output formats.

15. A processor for communications, comprising:

at least one interface operable to receive input image data and provide output image data for presentation on an electronic screen; and

at least one module operable to perform at least one post-processing function on the input image data to obtain the output image data, wherein the processor is operable to receive the input image data from at least one other module, and provide the output image data to a buffer to store the output image data prior to presentation on the electronic screen, and

wherein the at least one module is operable to scale input image data for a first image with a first coefficient, scale input image data for a second image with a second coefficient, and combine the scaled input image data for the first image with the scaled input image data for the second image to obtain the output image data for a composite image.

16. The processor of claim 15, wherein the at least one module is operable to perform flipping, texture mapping, and shading of the input image data.

17. The processor of claim 15, wherein the at least one module is operable to perform conversion from a first video format used for the input image data to a second video format used for the output image data.

18. The processor of claim 15, wherein the at least one module is operable to process the input image data to scale up or down an image in size.

19. The processor of claim 15, wherein the at least one module is operable to combine input image data for first and second images to obtain the output image data for a composite image.

20. The processor of claim 19, wherein the first image is a video image or a graphics image and the second image is text.

21. The processor of claim 15, wherein the at least one module is operable to alpha-blend two images to obtain a composite image.

22. The processor of claim 21, wherein the at least one module is operable to alpha-blend the composite image with a video image to obtain the output image data.

23. The processor of claim 15, wherein the at least one module is operable to perform transparency to superimpose a first image over a second image.

24. The processor of claim 15, wherein the at least one module is operable to perform alpha-blending of a first image and a second image.

25. The processor of claim 24, wherein an alpha value is selected for chroma keying.

26. The processor of claim 15, further comprising:

a programmable instruction processor operable to receive instructions and direct the at least one module to process the input image data in accordance with the received instructions.

27. The processor of claim 15, further comprising:

a memory to store the output image data until the buffer is ready to accept the output image data.

28. The processor of claim 15, wherein the at least one interface unit is operable to provide the output image data in an output format selected from among a plurality of possible output formats.

29. A processor for communications, comprising:

at least one interface operable to receive input image data and provide output image data for presentation on an electronic screen;

at least one module operable to perform at least one post-processing function on the input image data to obtain the output image data; and

a programmable instruction processor operable to receive instructions and direct the at least one module to process the input image data in accordance with the received instructions,

wherein the processor is operable to receive the input image data from at least one other module, and provide the output image data to a buffer to store the output image data prior to presentation on the electronic screen,

wherein the instructions are received in a list, and

wherein the instruction processor is operable to execute the instructions in the list until a termination condition is encountered.

30. The processor of claim 29, wherein the at least one module is operable to perform flipping, texture mapping, and shading of the input image data.

31. The processor of claim 29, wherein the at least one module is operable to perform conversion from a first video format used for the input image data to a second video format used for the output image data.

32. The processor of claim 29, wherein the at least one module is operable to process the input image data to scale up or down an image in size.

33. The processor of claim 29, wherein the at least one module is operable to combine input image data for first and second images to obtain the output image data for a composite image.

34. The processor of claim 33, wherein the first image is a video image or a graphics image and the second image is text.

35. The processor of claim 29, wherein the at least one module is operable to alpha-blend two images to obtain a composite image.

36. The processor of claim 35, wherein the at least one module is operable to alpha-blend the composite image with a video image to obtain the output image data.

37. The processor of claim 29, wherein the at least one module is operable to perform transparency to superimpose a first image over a second image.

38. The processor of claim 29, wherein the at least one module is operable to perform alpha-blending of a first image and a second image.

39. The processor of claim 38, wherein an alpha value is selected for chroma keying.

40. The processor of claim 29, further comprising:

a memory to store the output image data until the buffer is ready to accept the output image data.

41. The processor of claim 29, wherein the at least one interface unit is operable to provide the output image data in an output format selected from among a plurality of possible output formats.

42. A processor for communications, comprising:

at least one interface operable to receive input image data and provide output image data for presentation on an electronic screen; and

at least one module operable to perform at least one post-processing function on the input image data to obtain the output image data; and

a synchronization unit operable to determine timing for providing the output image data from the at least one interface unit to avoid causing visual artifacts on the electronic screen.

wherein the processor is operable to receive the input image data from at least one other module, and provide the output image data to a buffer to store the output image data prior to presentation on the electronic screen.

43. The processor of claim 42, wherein the synchronization unit is operable to determine the timing based on a vertical sync signal.

44. The processor of claim 42, wherein the output image data is retrieved and displayed on the screen based on a read pointer.

45. The processor of claim 42, wherein the at least one module is operable to perform flipping, texture mapping, and shading of the input image data.

46. The processor of claim 42, wherein the at least one module is operable to perform conversion from a first video format used for the input image data to a second video format used for the output image data.

47. The processor of claim 42, wherein the at least one module is operable to process the input image data to scale up or down an image in size.

48. The processor of claim 42, wherein the at least one module is operable to combine input image data for first and second images to obtain the output image data for a composite image.

49. The processor of claim 48, wherein the first image is a video image or a graphics image and the second image is text.

50. The processor of claim 42, wherein the at least one module is operable to alpha-blend two images to obtain a composite image.

51. The processor of claim 50, wherein the at least one module is operable to alpha-blend the composite image with a video image to obtain the output image data.

52. The processor of claim 42, wherein the at least one module is operable to perform transparency to superimpose a first image over a second image.

53. The processor of claim 42, wherein the at least one module is operable to perform alpha-blending of a first image and a second image.

54. The processor of claim 53, wherein an alpha value is selected for chroma keying.

55. The processor of claim 42, further comprising:

a programmable instruction processor operable to receive instructions and direct the at least one module to process the input image data in accordance with the received instructions.

56. The processor of claim 42, further comprising:

a memory to store the output image data until the buffer is ready to accept the output image data.

57. The processor of claim 42, wherein the at least one interface unit is operable to provide the output image data in an output format selected from among a plurality of possible output formats.

58. A processor for a communications device, comprising:

at least one interface operable to receive input image data and provide output image data for presentation on an electronic screen; and

at least one processing module operable to perform at least one post-processing function on the input image data to obtain the output image data,

wherein the processor is operable to provide an interface between at least one other processor providing the input image data for the electronic screen and a buffer used to store the output image data for the electronic screen,

wherein the input image data is in a YCrCb format with a luminance component and red and blue chrominance components, and

wherein the at least one processing module is operable to perform upsampling of the input image data for the red and blue chrominance components.

59. The processor of claim 58, wherein the at least one processing module is operable to perform flipping, texture mapping, and shading of the input image data.

60. The processor of claim 58, wherein the at least one processing module is operable to perform conversion from a first video format used for the input image data to a second video format used for the output image data.

61. The processor of claim 58, wherein the at least one processing module is operable to process the input image data to scale up or down an image in size.

62. The processor of claim 58, wherein the at least one processing module is operable to combine input image data for first and second images to obtain the output image data for a composite image.

63. The processor of claim 62, wherein the first image is a video image or a graphics image and the second image is text.

64. The processor of claim 58, wherein the at least one processing module is operable to alpha-blend two images to obtain a composite image.

65. The processor of claim 64, wherein the at least one processing module is operable to alpha-blend the composite image with a video image to obtain the output image data.

66. The processor of claim 58, wherein the at least one processing module is operable to perform transparency to superimpose a first image over a second image.

67. The processor of claim 58, wherein the at least one processing module is operable to perform alpha-blending of a first image and a second image.

68. The processor of claim 67, wherein an alpha value is selected for chroma keying.

69. The processor of claim 58, further comprising:

a programmable instruction processor operable to receive instructions and direct the at least one processing module to process the input image data in accordance with the received instructions.

70. The processor of claim 58, further comprising:

a memory to store the output image data until the buffer is ready to accept the output image data.

71. The processor of claim 58, wherein the at least one interface unit is operable to provide the output image data in an output format selected from among a plurality of possible output formats.

72. A processor for a communications device, comprising:

at least one interface operable to receive input image data and provide output image data for presentation on an electronic screen; and

at least one processing module operable to perform at least one post-processing function on the input image data to obtain the output image data,

wherein the processor is operable to provide an interface between at least one other processor providing the input image data for the electronic screen and a buffer used to store the output image data for the electronic screen,

wherein the at least one processing module is operable to scale input image data for a first image with a first coefficient, scale input image data for a second image with a second coefficient, and combine the scaled input image data for the first image with the scaled input image data for the second image to obtain the output image data for a composite image.

73. The processor of claim 72, wherein the at least one processing module is operable to perform flipping, texture mapping, and shading of the input image data.

74. The processor of claim 72, wherein the at least one processing module is operable to perform conversion from a first video format used for the input image data to a second video format used for the output image data.

75. The processor of claim 72, wherein the at least one processing module is operable to process the input image data to scale up or down an image in size.

76. The processor of claim 72, wherein the at least one processing module is operable to combine input image data for first and second images to obtain the output image data for a composite image.

77. The processor of claim 76, wherein the first image is a video image or a graphics image and the second image is text.

78. The processor of claim 72, wherein the at least one processing module is operable to alpha-blend two images to obtain a composite image.

79. The processor of claim 78, wherein the at least one processing module is operable to alpha-blend the composite image with a video image to obtain the output image data.

80. The processor of claim 72, wherein the at least one processing module is operable to perform transparency to superimpose a first image over a second image.

81. The processor of claim 72, wherein the at least one processing module is operable to perform alpha-blending of a first image and a second image.

82. The processor of claim 81, wherein an alpha value is selected for chroma keying.

83. The processor of claim 72, further comprising:

a programmable instruction processor operable to receive instructions and direct the at least one processing module to process the input image data in accordance with the received instructions.

84. The processor of claim 72, further comprising:

a memory to store the output image data until the buffer is ready to accept the output image data.

85. The processor of claim 72, wherein the at least one interface unit is operable to provide the output image data in an output format selected from among a plurality of possible output formats.

86. A processor for a communications device, comprising:

at least one interface operable to receive input image data and provide output image data for presentation on an electronic screen;

at least one processing module operable to perform at least one post-processing function on the input image data to obtain the output image data; and

a programmable instruction processor operable to receive instructions and direct the at least one processing module to process the input image data in accordance with the received instructions,

wherein the processor is operable to provide an interface between at least one other processor providing the input image data for the electronic screen and a buffer used to store the output image data for the electronic screen,

wherein the instructions are received in a list, and

wherein the instruction processor is operable to execute the instructions in the list until a termination condition is encountered.

87. The processor of claim 86, wherein the at least one processing module is operable to perform flipping, texture mapping, and shading of the input image data.

88. The processor of claim 86, wherein the at least one processing module is operable to perform conversion from a first video format used for the input image data to a second video format used for the output image data.

89. The processor of claim 86, wherein the at least one processing module is operable to process the input image data to scale up or down an image in size.

90. The processor of claim 86, wherein the at least one processing module is operable to combine input image data for first and second images to obtain the output image data for a composite image.

91. The processor of claim 86, wherein the first image is a video image or a graphics image and the second image is text.

92. The processor of claim 86, wherein the at least one processing module is operable to alpha-blend two images to obtain a composite image.

93. The processor of claim 92, wherein the at least one processing module is operable to alpha-blend the composite image with a video image to obtain the output image data.

94. The processor of claim 86, wherein the at least one processing module is operable to perform transparency to superimpose a first image over a second image.

95. The processor of claim 86, wherein the at least one processing module is operable to perform alpha-blending of a first image and a second image.

96. The processor of claim 95, wherein an alpha value is selected for chroma keying.

97. The processor of claim 86, further comprising:

a memory to store the output image data until the buffer is ready to accept the output image data.

98. The processor of claim 86, wherein the at least one interface unit is operable to provide the output image data in an output format selected from among a plurality of possible output formats.

99. A processor for a communications device, comprising:

at least one interface operable to receive input image data and provide output image data for presentation on an electronic screen

at least one processing module operable to perform at least one post-processing function on the input image data to obtain the output image data; and

a synchronization unit operable to determine timing for providing the output image data from the at least one interface unit to avoid causing visual artifacts on the electronic screen,

wherein the processor is operable to provide an interface between at least one other processor providing the input image data for the electronic screen and a buffer used to store the output image data for the electronic screen.

100. The processor of claim 99, wherein the synchronization unit is operable to determine the timing based on a vertical sync signal.

101. The processor of claim 99, wherein the output image data is retrieved and displayed on the screen based on a read pointer.

102. The processor of claim 99, wherein the at least one processing module is operable to perform flipping, texture mapping, and shading of the input image data.

103. The processor of claim 99, wherein the at least one processing module is operable to perform conversion from a first video format used for the input image data to a second video format used for the output image data.

104. The processor of claim 99, wherein the at least one processing module is operable to process the input image data to scale up or down an image in size.

105. The processor of claim 99, wherein the at least one processing module is operable to combine input image data for first and second images to obtain the output image data for a composite image.

106. The processor of claim 105, wherein the first image is a video image or a graphics image and the second image is text.

107. The processor of claim 99, wherein the at least one processing module is operable to alpha-blend two images to obtain a composite image.

108. The processor of claim 107, wherein the at least one processing module is operable to alpha-blend the composite image with a video image to obtain the output image data.

109. The processor of claim 99, wherein the at least one processing module is operable to perform transparency to superimpose a first image over a second image.

110. The processor of claim 99, wherein the at least one processing module is operable to perform alpha-blending of a first image and a second image.

111. The processor of claim 110, wherein an alpha value is selected for chroma keying.

112. The processor of claim 99, further comprising:

a programmable instruction processor operable to receive instructions and direct the at least one processing module to process the input image data in accordance with the received instructions.

113. The processor of claim 99, further comprising:

a memory to store the output image data until the buffer is ready to accept the output image data.

114. The processor of claim 99, wherein the at least one interface unit is operable to provide the output image data in an output format selected from among a plurality of possible output formats.