Graphics display system with anti-flutter filtering and vertical scaling feature

• US 7,554,562 B2
• Filed: 12/18/2007
• Issued: 06/30/2009
• Est. Priority Date: 11/09/1998
• Status: Expired due to Fees

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Kranawetter, Greg A., Patterson, James T., Xie, Xiaodong
• Primary Examiner(s): Sajous; Wesner
• Application Number:
  US11/959,315
• Publication Number:
  US 20080094416A1
• Time in Patent Office: 560 Days
• Field of Search: 345/611, 345589-592, 345/547, 345/545, 345/660, 345/554, 345600-601, 345/618, 345/419, 345/519, 345/501, 348/441, 348/447, 348/536, 348/554, 348/497, 348/571, 715/781, 715/798, 715/800, 382/254, 382/276, 382260-265, 382/274
• US Class Current: 345/629
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 : using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440263 : by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/04 : Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0122 : the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Claims

1. One or more circuits for processing graphics and video images to produce a blended image, the one or more circuits comprising:

at least one processor operable to;

receive a video image;

blend a plurality of graphics images using a plurality of alpha values associated with the graphics images to generate a blended graphics image for storage in at least one memory,

process the graphics images and/or the blended graphics image to place the blended graphics image in a format suitable for blending with the video image, and

blend the blended graphics image with the video image using the alpha values and/or at least one value derived from the alpha values.

2. The one or more circuits according to claim 1, wherein the at least one processor is operable to process the graphics images and/or the blended graphics image using polyphase filtering.

3. The one or more circuits according to claim 2, wherein the at least one processor is operable to anti-flutter filter the graphics images and/or the blended graphics image using polyphase filtering.

4. The one or more circuits according to claim 2, wherein the at least one processor is operable to scale the graphics images and/or the blended graphics image using polyphase filtering.

5. The one or more circuits according to claim 4, wherein the at least one processor is operable to scale the graphics images and/or the blended graphics image vertically and/or horizontally.

6. The one or more circuits according to claim 2, wherein the polyphase filtering is programmable.

7. The one or more circuits according to claim 2, wherein the at least one processor is operable to polyphase filter in a field mode wherein every other line of the graphics images and/or the blended graphics image is processed during filtering.

8. The one or more circuits according to claim 2, wherein the at least one processor is operable to polyphase filter in a frame mode wherein every line of the graphics images and/or the blended graphics image is processed during filtering.

9. The one or more circuits according to claim 6, wherein the at least one memory comprises at least one of horizontal coefficients and vertical coefficients for programming the polyphase filtering.

10. The one or more circuits according to claim 1 wherein the at least one processor is operable to convert graphics data format of at least one of the plurality of graphics images prior to blending the graphics images such that the plurality of graphics images have a common graphics data format.

11. One or more circuits for a communications device, the one or more circuits comprising:

at least one processor operably coupled to an interface for receiving video image data, the at least one processor operable to, at least;

pre-process the video image data to produce a video image;

render a plurality of graphics images from graphics image data stored in memory;

generate a combined image from the plurality of graphics images and the video image; and

post-process the combined image to produce output image data, wherein post-processing comprises applying a filter to each pixel of the output image data using one or more pixels of the output image data that are adjacent to the pixel in one or both of the vertical axis and horizontal axis.

12. The one or more circuits according to claim 11 wherein the video image data is inter-frame coded.

13. The one or more circuits according to claim 11 wherein pre-processing produces YUV formatted image data having separate luminance and chrominance components.

14. The one or more circuits according to claim 11 wherein pre-processing comprises resizing the video image data to scale an image up or down in size.

15. The one or more circuits according to claim 14 wherein pre-processing comprises storing the pre-processed video image in memory.

16. The one or more circuits according to claim 11 wherein pre-processing comprises adjusting a sample rate of the video image data.

17. The one or more circuits of claim 11 wherein the at least one processor is operable to convert image data between a first color space and a second color space.

18. The one or more circuits of claim 17 wherein one of the first color space and the second color space is YUV (luma chroma) format and the other of the first color space and the second color space is RGB (Red-Green-Blue) format.

19. The one or more circuits of claim 11 wherein generating a combined image comprises first blending the plurality of graphics images according to an associated plurality of alpha values to form a combined graphics image, and second blending the combined graphics image with the video image.

20. The one or more circuits of claim 19 wherein the plurality of alpha values comprises a single alpha value for each graphics image.

21. The one or more circuits of claim 19 wherein the plurality of alpha values comprises a separate alpha value for each pixel of a graphics image.

22. The one or more circuits of claim 11 wherein the graphics image data represents a plurality of three dimensional graphics images.

23. The one or more circuits of claim 11 wherein the graphics image data comprises a plurality of windows, each window comprising one of the plurality of graphics images.

24. The one or more circuits of claim 23 wherein each window has an associated alpha value that is used during alpha blending all pixels in the window.

25. The one or more circuits of claim 11 wherein the memory is physically separate from the one or more circuits.

26. The one or more circuits of claim 11 wherein the filter is a low-pass filter.

27. The one or more circuits according to claim 11 wherein post-processing comprises resizing the output image data to scale an image up or down in size.

28. The one or more circuits according to claim 27 wherein post-processing comprises retrieving the combined image from memory.

29. The one or more circuits of claim 11 wherein post-processing the combined image comprises converting between a first color space and a second color space.

30. The one or more circuits of claim 29 wherein one of the first color space and the second color space is YUV (luma chroma) format and the other of the first color space and the second color space is RGB (Red-Green-Blue) format.

31. The one or more circuits of claim 11 wherein the at least one processor is operable to, at least:

transmit the output image data directly to a display device without buffering the output image data.

32. The one or more circuits of claim 11 wherein the at least one processor is operable to, at least:

transmit the output image data to a display buffer operably coupled to the at least one processor.

33. The one or more circuits of claim 32 wherein the display buffer holds one or more frames of pixels.

34. The one or more circuits of claim 11 wherein the at least one processor is operable to, at least:

receive digitized audio information for one or both of storage and playback.

35. One or more circuits for a communications device, the one or more circuits comprising:

at least one processor operably coupled to at least one memory having stored therein graphics image data and video image data, the at least one processor operable to, at least;

render a graphics image from the graphics image data;

pre-process the video image data to produce a video image formatted for combining with the graphics image;

combine the video image with the graphics image to produce a combined image, using the at least one alpha value; and

post-process the combined image to produce output image data in the at least one memory, wherein post-processing comprises applying a filter to each pixel of the output image data using one or more pixels of the output image data that are adjacent to the pixel in one or both of the vertical axis and horizontal axis.

36. The one or more circuits according to claim 35 wherein the video image data is inter-frame coded.

37. The one or more circuits according to claim 35 wherein pre-processing produces YUV formatted image data having separate luminance and chrominance components.

38. The one or more circuits according to claim 35 wherein pre-processing comprises resizing the video image data to scale an image up or down in size.

39. The one or more circuits according to claim 38 wherein pre-processing comprises storing the pre-processed video image in memory.

40. The one or more circuits according to claim 35 wherein pre-processing comprises adjusting a sample rate of the video image data.

41. The one or more circuits of claim 35 wherein the at least one processor is operable to convert between a first color space and a second color space.

42. The one or more circuits of claim 41 wherein one of the first color space and the second color space is YUV (luma chroma) format and the other of the first color space and the second color space is RGB (Red-Green-Blue) format.

43. The one or more circuits of claim 35 wherein rendering a graphics image from the graphics image data comprises combining blending the plurality of graphics images according to an associated plurality of alpha values, and then combining the rendered graphics image with the video image.

44. The one or more circuits of claim 43 wherein the plurality of alpha values comprises a single alpha value for each graphics image.

45. The one or more circuits of claim 43 wherein the plurality of alpha values comprises a separate alpha value for each pixel of a graphics image.

46. The one or more circuits of claim 35 wherein the graphics image data represents a plurality of three dimensional graphics images.

47. The one or more circuits of claim 35 wherein the graphics image data comprises a plurality of windows, each window comprising one of the plurality of graphics images.

48. The one or more circuits of claim 47 wherein each window has an associated alpha value that is used during alpha blending all pixels in the window.

49. The one or more circuits of claim 35 wherein the at least one memory is physically separate from the one or more circuits.

50. The one or more circuits of claim 35 wherein the filter is a low-pass filter.

51. The one or more circuits according to claim 35 wherein post-processing comprises resizing the output image data to scale an image up or down in size.

52. The one or more circuits according to claim 51 wherein post-processing comprises retrieving the combined image from the at least one memory.

53. The one or more circuits of claim 35 wherein post-processing the combined image comprises converting between a first color space and a second color space.

54. The one or more circuits of claim 53 wherein one of the first color space and the second color space is YUV (luma chroma) format and the other of the first color space and the second color space is RGB (Red-Green-Blue) format.

55. The one or more circuits of claim 35 wherein the at least one processor is operable to, at least:

transmit the output image data directly to a display device without buffering the output image data.

56. The one or more circuits of claim 35 wherein the at least one processor is operable to, at least:

transmit the output image data to a display buffer operably coupled to the at least one processor.

57. The one or more circuits of claim 56 wherein the display buffer holds one or more frames of pixels.

58. The one or more circuits of claim 35 wherein the at least one processor is operable to, at least:

receive digitized audio information for one or both of storage and playback.