Method and circuit for performing correlated double sub-sampling (CDSS) of pixels in an active pixel sensor (APS) array

• US 7,554,584 B2
• Filed: 02/28/2005
• Issued: 06/30/2009
• Est. Priority Date: 03/16/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Suhun
• Primary Examiner(s): Ho; Tuan V
• Assistant Examiner(s): WANG, KENT F
• Application Number:
  US11/068,205
• Publication Number:
  US 20050206752A1
• Time in Patent Office: 1,583 Days
• Field of Search: 348/241, 348/294, 341/155, 382/103, 711/217, 250/208.1
• US Class Current: 348/241
• CPC Class Codes: H04N 25/47 Image sensors with pixel address output; Event-driven image sensors; Selection of pixels to be read out based on image data
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/673 by using reference sources
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

A method and circuit for performing Correlated Double Sub-Sampling (CDSS) of pixels in an active pixel sensor (APS) array. The method and the apparatus subsamples a plurality (L²) of pixels by: storing L² analog reset charges output from the L² pixels into a first set of (N²) storage capacitors, and combining the (L²) reset charges; storing L² analog image signal charges output from the L² pixels into a second set of (N²) storage capacitors, and combining the (L²) image charges; and then obtaining a differential voltage (VS-VR) by subtracting (in the analog-domain) the voltage (VR) represented by the combined (L²) reset charges from the voltage (VS) represented by the combined (L²) image signal charges. When L equals one, the circuit performs conventional Correlated Double Sampling CDS upon the one pixel.

Claims

1. An image sensor comprising a plurality of pixels arranged in rows and columns, each column of pixels being switchably connected to at least two reset charge storage capacitors for storing at least two reset charges and to at least two image signal charge storage capacitors for storing at least two image signal charges, wherein at least one of the at least two reset charge storage capacitors in each column is configured to be connected at a node in series to at least one of the at least two image signal charge storage capacitors in the same column,

wherein at least two reset charge storage capacitors are switchably connected to each other to generate an averaged reset charge for at least two pixels in the same column.

2. The image sensor according to claim 1, further including a switch connected between the nodes corresponding to two different columns of pixels.

3. The image sensor according to claim 2, wherein the switch is configured to alternately perform a first averaging operation using at least two reset charges from the two different columns to generate an averaged reset charge and a second averaging operation using at least two image charges from the two different columns to generate an averaged image signal charge.

4. The image sensor according to claim 3, wherein the first and second averaging operations are sequentially performed in the analog domain.

5. The image sensor according to claim 3, further including an analog subtractor, for subtracting a first voltage corresponding to an averaged reset charge from a second voltage corresponding to an averaged image signal charge to generate an averaged pixel data voltage stored in a capacitance.

6. The image sensor according to claim 5, further including an analog to digital converter (ADC) including a counter for carrying out analog to digital conversion of the averaged pixel data voltage.

7. The image sensor according to claim 6, wherein the capacitance storing the averaged pixel data voltage is switchably connected between a bias voltage source and the ADC.

8. The image sensor according to claim 7, wherein the bias voltage source is at a first voltage level during the first and second averaging operations and ramped up towards a second voltage level during the ADC operation.

9. The image sensor according to claim 3, further comprising an averaging circuit including the switch connected between two nodes corresponding to two different columns.

10. The image sensor according to claim 1, wherein the at least two reset charge storage capacitors in each column are configured to be switchably connected in parallel with each other and wherein the at least two image signal charge storage capacitors in each column are configured to be switchably connected in parallel with each other.

11. The image sensor according to claim 1, wherein one of the at least two reset charge storage capacitors in a first column and one of the at least two image signal charge storage capacitors in the first column are connected to each other at the node without a switch being disposed between them.

12. The image sensor according to claim 1, wherein the at least two reset charge storage capacitors in each column comprise four reset charge storage capacitors, and wherein the at least, two image signal charge storage capacitors in each column comprise four image signal charge storage capacitors, and wherein only three of the four reset charge storage capacitors are connected to the node through sample-holding switches, and wherein only three of the four image signal charge storage capacitors in each column are connected to the node through sample-holding switches.

13. The image sensor according to claim 1, wherein a sample-holding switch is disposed between the node and each of all of the at least two reset charge storage capacitors in a first column;

and

wherein a sample-holding switch is disposed between the node and each of all of the at least two image signal charge storage capacitors in the first column.

14. The image sensor of claim 1, wherein at least two image signal charge storage capacitors are switchably connected to each other to generate an averaged image signal charge for at least two pixels in the same column.

15. A method of subsampling N² pixels in an active pixel sensor (APS) array, the method comprising:

sequentially storing into N reset charge storage capacitors N pixel reset charges received from N pixels in the same first column of the APS array, wherein the N reset charge storage capacitors are switchably connected to each other in parallel between a first node and a second node; and

closing no more than N−

1 reset charge-holding switches connected to the N reset charge storage capacitors between the first node and the second node; and

closing a row-direction averaging switch disposed between the first node and a second set of N reset charge storage capacitors N corresponding to a second column of the APS array,

wherein the N reset charge storage capacitors are connected to each other in parallel when the N−

1 reset charge-holding switches are closed, such that an averaged reset charge for N pixels in the first column in generated.

16. The method of claim 15, further comprising combining the pixel reset charges stored in the first and second capacitors among the N reset charge storage capacitors by connecting the first and second reset charge storage capacitors in parallel to each other.

17. The method of claim 15, further comprising combining pixel signal charges stored in the first and second capacitors among a set of N image signal charge storage capacitors.

18. The method of claim 17, wherein combining the pixel signal charges stored in the first and second image signal charge storage capacitors includes connecting the first and second image signal charge storage capacitors in parallel to each other.

19. The method of claim 16, further comprising storing in third and fourth capacitors among the set of reset charge storage capacitors third and fourth pixel reset charges respectively received from third and fourth pixels in a second row and in the first and second columns of the APS array, wherein storing the pixel reset charge from the third pixel in the third reset charge storage capacitor includes the substeps of:

receiving in each of the first and third reset charge storage capacitors the pixel reset charge from the first pixel; and

afterwards

opening a holding switch connected to the first reset charge storage capacitor to hold in the first reset charge storage capacitor the pixel reset charge received from the first pixel; and

afterwards

receiving in the third reset charge storage capacitor the pixel reset charge from the third pixel.

20. The method of claim 19, further comprising combining the pixel reset charges stored in the third and fourth reset charge storage capacitors before opening the holding switch connected to the first reset charge storage capacitor.

21. The method of claim 19, further comprising:

further comprising storing in third and fourth capacitors among the set of signal charge storage capacitors third and fourth pixel signal charges respectively received from the third and fourth pixels; and

combining the pixel signal charges stored in the third and fourth signal charge storage capacitor.

22. The method of claim 21, further including a subtraction operation in the analog domain wherein a difference voltage is obtained by connecting the first signal charge storage capacitor in series with the first reset charge storage capacitor.

23. The method of claim 22, further including performing an analog to digital conversion (ADC) of the difference voltage.

24. The method of claim 22, further comprising performing an analog to digital conversion (ADC) by ramping up a bias voltage connected to the series-connected first signal charge storage capacitor and first reset charge storage capacitor.

25. The method of claim 24, wherein the bias source is at a low voltage level during the receiving of charges in the storage capacitors and is ramped upwards towards a high voltage level during the ADC.

26. The method of claim 15, wherein the four pixels are arrayed in two rows and in two columns, and a first averaging operation includes:

obtaining a first same-row average of two reset charges from a first pair of pixels in the first row, and then obtaining a second same-row average of two reset charges from a second pair of pixels in the second row; and

then averaging the first same-row average with the second same-row average.

27. The method of claim 15, wherein sequentially storing into N reset charge storage capacitors N pixel reset charges includes storing in the first and second capacitors among the N reset charge storage capacitors the pixel reset charges received from the first and second pixels in the first column, and includes the substeps of:

closing a first one of the N−

1 switches connected between the first node and the first capacitor;

receiving in each of the first and second capacitors the pixel reset charge from the first pixel; and

afterwards opening the first one of the N−

1 switches connected between the first node and the first capacitor to hold within the first capacitor the pixel reset charge received from the first pixels in the first column; and

then

receiving in the second capacitor the pixel reset charge from the second pixel in the first column.

28. The method of claim 15 further comprising:

sequentially storing into N image signal charge storage capacitors N image signal charges received from N pixels in the same first column of the APS array, wherein the N image signal charge storage capacitors are switchably connected to each other in parallel between the first node and a third node; and

closing no more than N−

1 image signal charge-holding switches connected to the N image signal charge storage capacitors between the first node and the third node.

29. The method of claim 15, further comprising storing in third and fourth capacitors among the set of image signal charge storage capacitors third and fourth image signal charges respectively received from third and fourth pixels in a second row and in the first and second columns of the APS array, wherein storing the image signal charge from the third pixel in the third image signal charge storage capacitor includes the substeps of:

receiving in each of the first and third image signal charge storage capacitors the image signal charge from the first pixel; and

afterwards

opening a holding switch connected to the first image signal charge storage capacitor to hold in the first image signal charge storage capacitor the image signal charge received from the first pixel; and

afterwards

receiving in the third image signal charge storage capacitor the image signal charge from the third pixel.

30. An image sensor comprising:

an array of pixels arranged in a plurality of rows and a plurality of columns, every pixel in each column of pixels is operatively connected to an averaging unit, wherein each averaging unit includes a first and second storage capacitors for storing reset charges from a first pixel and from a second pixel, and further includes third and fourth storage capacitors for storing analog image signal charges from the first pixel and from the second pixel, wherein at least one of the at least two reset charge storage capacitors in each column is configured to be connected at a node in series to at least one of the at least two image signal charge storage capacitors in the same column,

wherein the first and second storage capacitors are switchably connected to each other to generate an averaged reset charge for the first and second pixels in the same column.

31. The image sensor of claim 30, further comprising a first averaging switch configured to combine the reset charges stored in at least two averaging units.

32. The image sensor of claim 31, wherein the first averaging switch is further configured to combine the image signal charges stored in the same at least two averaging units.

33. The image sensor of claim 30, wherein each averaging unit further includes:

an Nth storage capacitor for storing image signal charge from an Nth pixel and a 2Nth storage capacitor for storing analog reset data charge from the Nth pixel.

34. The image sensor of claim 30, further comprising an analog to digital converter (ADC) for each column, for carrying out analog to digital conversion of the plurality of outputs from the averaging units.

35. The image sensor of claim 34, wherein each analog to digital convener (ADC) is adapted to perform in-parallel the analog to digital conversion of the output from one of the averaging units.

36. The image sensor of claim 30, wherein each averaging unit is connected between a bias voltage source and an input of its corresponding ADC.

37. The image sensor of claim 30, wherein the bias voltage source is at a first voltage level during the averaging unit'"'"'s operation and ramps up towards a second voltage level during the ADC operation, the first voltage level being different from the second voltage level.

38. The image sensor of claim 30, wherein each averaging unit further includes a reset column-averaging switch disposed between the first and second storage capacitors for averaging reset charges from pixels in the same column.

39. The image sensor of claim 30, wherein each averaging unit further includes an image signal column-averaging switch disposed between the third and fourth storage capacitors for averaging image signal charges from pixels in the same column.

40. The image sensor of claim 30, wherein the third and fourth storage capacitors are switchably connected to each other to generate an averaged image signal charge for the first and second pixels in the same column.

41. A method of subsampling N² pixels in an array of pixels arranged in a plurality of rows and a plurality of columns, each pixel being adapted to output a reset voltage and an image signal voltage, the method comprising the steps of:

storing the plurality of reset voltages output from the N² pixels into a first set of storage capacitors and combining the plurality of reset voltages stored in the first set of storage capacitors;

storing a plurality of image signal voltages output from the plurality of N² pixels into a second set of storage capacitors and combining the plurality of image signal voltages stored in the second set of storage capacitors; and

connecting at least one storage capacitor among the first set of storage capacitors in-series with at least one storage capacitor among the second set of storage capacitors,

wherein the storage capacitors in the first set are switchably connected to each other to generate an averaged reset charge for the plurality of pixels in the same column.

42. The method of claim 41, further comprising, detecting the voltage across the series-connected storage capacitors among the first and second sets of storage capacitors.

43. The method of claim 41, further comprising, digitally quantizing the voltage across the series-connected storage capacitors among the first and second sets of storage capacitors.

44. The method of claim 41, wherein the storage capacitors in the second set are switchably connected to each other to generate an averaged image signal charge for the plurality of pixels in a same column.

45. A method of subsampling N² pixels arrayed in N columns and N rows of an active pixel sensor (APS) array, each pixel being adapted to output a reset voltage and an image signal voltage, the method comprising the steps of:

storing the reset voltage of the first pixel in the first row as a first charge in a first capacitor and storing the reset voltage of the second pixel in the first row as a second charge in a second capacitor; and

then immediately combining the first and second charges into a first row-averaged reset charge; and

afterwards

storing the reset voltage of the first pixel in the second row as a fifth charge in a fifth capacitor and storing the reset voltage of the second pixel in the second row as a sixth charge in a sixth capacitor; and

then immediately combining the fifth and sixth charges into a second row-averaged reset charge; and

combining the first row-averaged reset charge and the second row-averaged reset charge into a subsampled reset charge,

wherein the first and fifth capacitors are switchably connected to each other to generate an averaged reset charge for the pixels of the first and second rows in the same column.

46. The method of claim 45, storing the reset voltage of the first pixel in the first row as a first charge in a first capacitor includes the substeps of:

receiving in each of the first and fifth capacitors the reset voltage from the first pixel in the first row and

opening a switch connected to the first capacitor to hold in the first capacitor the reset voltage received from the first pixel in the first row; and

and storing the reset voltage of the first pixel in the second row as a fifth charge in a fifth capacitor includes keeping open the switch connected to the first capacitor and receiving in the fifth capacitor the reset voltage from the first pixel in the second row.