Capacitor array management

• US 7,554,789 B2
• Filed: 06/29/2006
• Issued: 06/30/2009
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, Hung-I
• Primary Examiner(s): Thomas; Eric
• Assistant Examiner(s): Sinclair; David M
• Application Number:
  US11/427,387
• Publication Number:
  US 20080002332A1
• Time in Patent Office: 1,097 Days
• Field of Search: 361/328, 361/329
• US Class Current: 361/328
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A capacitor array comprising a plurality of unit capacitors, each having first and second electrode plates. The first electrode plates are commonly connected via first routings. The second electrode plates are grouped and connected to a plurality of nodes via second routings. The second routings connected to one node and another do not overlap in the capacitor array. The second electrode plates connected to the same node conglomerate as a group and no second electrode plate connected to another node is located in the group.

Claims

1. A capacitor comprising identical capacitor arrays arranged symmetrically in a horizontal orientation, and each of the capacitor arrays comprising:

a plurality of unit capacitors, each having first and second electrode plates;

wherein the first electrode plates are connected via first routings, and the second electrode plates are grouped and connected to a plurality of nodes via second routings, wherein second routings connected to one node and another do not overlap in the capacitor array, and all of the second electrode plates connected to the same node conglomerate as a sub-capacitor, and no second electrode plate connected to another node is located in the sub-capacitor;

wherein the second routings of the capacitor arrays are routed out to a plurality of signal rails, respectively associated with one of the nodes, between the capacitor arrays, and the signal rails are formed with a conducting layer other than a conducting layer for the second routings of the second electrode plates.

2. The capacitor as claimed in claim 1, wherein the nodes respectively receive a binary signal.

3. The capacitor as claimed in claim 1, wherein the relationship of capacitance associated with the nodes obeys an exponent of two and differs from node to node.

4. The capacitor as claimed in claim 1, wherein the nodes are arranged on the same side of the capacitor array.

5. The capacitor as claimed in claim 1, wherein half of the unit capacitors are grouped together and have a sawtooth-shaped edge along a diagonal of the capacitor array, half of the unit capacitors from the other half are grouped together, and so forth until a group comprising a single unit cell is formed.

6. The capacitor as claimed in claim 1, further comprising a plurality of dummy capacitors uniformly distributed around the periphery.

7. The capacitor as claimed in claim 1, wherein the first routings are formed with a first metal layer and the second routings a second metal layer.

8. A capacitor comprising identical capacitor arrays arranged symmetrically in a vertical orientation, and each of the capacitor arrays comprising:

a plurality of unit capacitors, each having first and second electrode plates;

wherein the first electrode plates are connected via first routings, and the second electrode plates are grouped and connected to a plurality of nodes via second routings, wherein second routings connected to one node and another do not overlap in the capacitor array, and all of the second electrode plates connected to the same node conglomerate as a sub-capacitor, and no second electrode plate connected to another node is located in the sub-capacitor;

wherein the second routings of the capacitor arrays are routed out to a plurality of signal rails, respectively associated with one of the nodes, between the capacitor arrays; and

the signal rails are formed with a conducting layer other than a conducting layer for the second routings of the second electrode plates.

9. The capacitor as claimed in claim 8, wherein the nodes respectively receive a binary signal.

10. The capacitor as claimed in claim 8, wherein the relationship of capacitance associated with the nodes obeys an exponent of two and differs from node to node.

11. The capacitor as claimed in claim 8, wherein the nodes are arranged on the same side of the capacitor array.

12. The capacitor as claimed in claim 8, wherein half of the unit capacitors are grouped together and have a sawtooth-shaped edge along a diagonal of the capacitor array, half of the unit capacitors from the other half are grouped together, and so forth until a group comprising a single unit cell is formed.

13. The capacitor as claimed in claim 8, further comprising a plurality of dummy capacitors uniformly distributed around the periphery.

14. The capacitor as claimed in claim 8, wherein the first routings are formed with a first metal layer and the second routings a second metal layer.

15. A capacitor layout technique, comprising:

providing a capacitor comprising identical capacitor arrays;

disposing the capacitor arrays symmetrically in a horizontal orientation; and

providing a plurality of unit capacitors for each of the capacitor arrays, each of the unit capacitors having first and second electrode plates, wherein the first electrode plates are commonly connected via first routings and the second electrode plates are connected to a plurality of nodes via second routings, and the step of providing the unit capacitors comprising;

for each of the capacitor arrays, dividing the second electrode plates into groups each associated with one of the nodes such that the second routings connected to one node and another do not overlap in the capacitor array, and all of the second electrode plates connected to the same node conglomerate as a sub-capacitor, and no second electrode plate connected to another node is located in the sub-capacitor; and

wherein the second routings of the capacitor arrays are routed out to a plurality of signal rails, respectively associated with one of the nodes, between the capacitor arrays; and

the signal rails are formed with a conducting layer other than a conducting layer for the second routings of the second electrode plates.

16. The capacitor layout technique as claimed in claim 15, wherein dividing the second electrode plates into groups further comprises grouping half of the unit capacitors as a first group of the sub-capacitors, grouping half of the unit capacitors from the other half as a second group of the sub-capacitors, and repeating such grouping until a group comprising a single unit cell is formed;

wherein the first group of the sub-capacitors has a sawtooth-shaped edge along a diagonal of the capacitor array.

17. A capacitor layout technique, comprising:

providing a capacitor comprising identical capacitor arrays;

disposing the capacitor arrays symmetrically in a vertical orientation; and

providing a plurality of unit capacitors for each of the capacitor arrays, each of the unit capacitors having first and second electrode plates, wherein the first electrode plates are commonly connected via first routings and the second electrode plates are connected to a plurality of nodes via second routings, and the step of providing the unit capacitors comprises;

for each of the capacitor arrays, dividing the second electrode plates into groups each associated with one of the nodes such that the second routings connected to one node and another do not overlap in the capacitor array, and all of the second electrode plates connected to the same node conglomerate as a sub-capacitor, and no second electrode plate connected to another node is located in the sub-capacitor; and

wherein the second routings of the capacitor arrays are routed out to a plurality of signal rails, respectively associated with one of the nodes, between the capacitor arrays; and

the signal rails are formed with a conducting layer other than a conducting layer for the second routings of the second electrode plates.

18. The capacitor layout technique as claimed in claim 17, wherein dividing the second electrode plates into groups further comprises grouping half of the unit capacitors as a first group of the sub-capacitors, grouping half of the unit capacitors from the other half as a second group of the sub-capacitors, and so forth until a group comprising a single unit cell is formed;

wherein the first group of the sub-capacitors has a sawtooth-shaped edge along a diagonal of the capacitor array.