Flash memory device employing disturbance monitoring scheme
First Claim
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1. A flash memory device, comprising:
- a memory cell array comprising a plurality of NAND strings respectively connected to a plurality of bit lines, and further comprising first and second disturbed strings respectively coupled to first and second disturbed bit lines, wherein each of the plurality of NAND strings comprises a plurality of memory cells and each of the first and second disturbed strings comprises a plurality of memory cells;
a row selector adapted to drive word lines respectively connected to the plurality of memory cells within each of the plurality of NAND strings and within the first disturbed string;
a page buffer circuit electrically connected to the bit lines and the first and second disturbed bit lines;
a bias circuit configured to drive a common gate line connected to the memory cells in the second disturbed string; and
a controller configured to control operation of the row selector, the page buffer circuit, and the bias circuit;
wherein during a program operation, the controller operates to control the page buffer circuit and the bias circuit such that one or more memory cells in the first disturbed string assume states indicative of program voltage disturbance and one or more memory cells in the second disturbed string assume states indicative of pass voltage disturbance.
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Abstract
A flash memory device comprises a memory cell array including a plurality of NAND strings respectively connected to a plurality of bit lines, and further comprising a disturbed string coupled to a disturbed bit line. In a program operation of the flash memory device, a voltage level of the disturbed bit line is detected to detect program or pass voltage disturbance in the memory cell array.
64 Citations
38 Claims
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1. A flash memory device, comprising:
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a memory cell array comprising a plurality of NAND strings respectively connected to a plurality of bit lines, and further comprising first and second disturbed strings respectively coupled to first and second disturbed bit lines, wherein each of the plurality of NAND strings comprises a plurality of memory cells and each of the first and second disturbed strings comprises a plurality of memory cells; a row selector adapted to drive word lines respectively connected to the plurality of memory cells within each of the plurality of NAND strings and within the first disturbed string; a page buffer circuit electrically connected to the bit lines and the first and second disturbed bit lines; a bias circuit configured to drive a common gate line connected to the memory cells in the second disturbed string; and a controller configured to control operation of the row selector, the page buffer circuit, and the bias circuit; wherein during a program operation, the controller operates to control the page buffer circuit and the bias circuit such that one or more memory cells in the first disturbed string assume states indicative of program voltage disturbance and one or more memory cells in the second disturbed string assume states indicative of pass voltage disturbance. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A flash memory device comprising:
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a memory cell array including a plurality of NAND strings respectively connected to a plurality of bit lines and a disturbed string connected to a disturbed bit line, wherein each of the plurality of NAND strings comprises a plurality of memory cells and the disturbed string comprises a plurality of memory cells; a row selector adapted to drive word lines respectively connected to the plurality of memory cells within each of the plurality of NAND strings and within the disturbed string; a page buffer circuit electrically connected to the bit lines and the disturbed bit line; and a controller configured to control operation of the row selector and the page buffer circuit; wherein during every program operation of the plurality of NAND strings, the controller controls the page buffer circuit to drive the disturbed bit line with a power source voltage. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A flash memory device, comprising:
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a memory cell array including a plurality of NAND strings respectively connected to a plurality of bit lines and a disturbed string connected to a disturbed bit line, wherein each of the plurality of NAND strings comprises a plurality of memory cells and the disturbed string comprises a plurality of memory cells; a row selector adapted to drive word lines respectively connected to the plurality of memory cells within each of the plurality of NAND strings; a page buffer circuit electrically connected to the bit lines and the disturbed bit line; a bias circuit configured to drive a common gate line connected to the memory cells in the disturbed string; and a controller configured to control operation of the row selector and the page buffer circuit; wherein during a program operation, the controller controls the page buffer circuit and the bias circuit such that one or more memory cells in the disturbed string assume states indicative of pass voltage disturbance. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A method for operating a flash memory device comprising a memory cell array comprising a plurality of NAND strings respectively connected to a plurality of bit lines, and further comprising a first disturbed string coupled to a first disturbed bit line, the method comprising:
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during every program operation of the plurality of NAND strings, driving the disturbed bit line with a power source voltage; and
,detecting a voltage level of the first disturbed bit line to detect program voltage disturbance in the memory cell array. - View Dependent Claims (37)
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38. A method for operating a flash memory device comprising a memory cell array comprising a plurality of NAND strings respectively connected to a plurality of bit lines, and further comprising a disturbed string comprising a plurality of memory cells, wherein the disturbed string is coupled to a disturbed bit line, the method comprising:
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driving a common gate line connected to gates of the memory cells in the disturbed string using a bias circuit; and
,detecting a voltage level of the disturbed bit line to detect pass voltage disturbance in the memory cell array.
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Specification