Three-dimensional memory devices and methods of manufacturing and operating the same

• US 7,554,873 B2
• Filed: 03/21/2006
• Issued: 06/30/2009
• Est. Priority Date: 03/21/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Shih, Yen Hao, Lee, Ming Hsiu
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/385,360
• Publication Number:
  US 20060233082A1
• Time in Patent Office: 1,197 Days
• Field of Search: 365/230.03, 365/63
• US Class Current: 365/230.03
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory device includes a plurality of planes of memory arrays, each memory array including a plurality of memory cells. The memory device also includes a plurality of word lines and bit lines coupled to the memory cells in each plane, and at least one transistor to select at least one of the memory arrays.

Claims

1. A memory device comprising:

a plurality of planes of memory arrays, each memory array including a plurality of memory cells;

a plurality of word lines and bit lines coupled to the memory cells in each plane; and

at least one transistor to select at least one of the memory arrays.

2. The memory device of claim 1, further comprising:

a decoder to activate the at least one transistor.

3. The memory device of claim 2, wherein the decoder selects one of the memory arrays in a horizontal plane.

4. The memory device of claim 2, wherein at least one transistor is located on the same or different plane as the selected memory array.

5. The memory device of claim 1, wherein the memory cells include a cross point memory device or a transistor memory device.

6. A memory device comprising:

at least two layers of memory arrays each containing at least four memory cells;

at least two word lines in each layer coupled with the memory cells of the corresponding layer;

at least two bit lines in each layer coupled with the memory cells of the corresponding layer; and

at least a set of layer-selecting transistors for each layer, each set of the layer-selecting transistors being coupled to the memory cells of the corresponding layer.

7. The memory device of claim 6, wherein each set of the layer-selecting transistors is coupled to the memory cells of the corresponding layer through the bit lines coupled to the memory cells of that layer.

8. The memory device of claim 6, wherein each set of the layer-selecting transistors is coupled to memory cells of the corresponding layer through the word lines coupled to the memory cells of the layer.

9. The memory device of claim 6, wherein each set of the layer-selecting transistors is controlled by a plane decoding signal.

10. The memory device of claim 6, wherein at least one set of the layer-selecting transistors is placed on the corresponding layer along with the memory cells of that layer.

11. The memory device of claim 6, wherein at least one set of the layer-selecting transistors is placed on at least one of a ground layer and a raised layer of the memory device.

12. The memory device of claim 6, wherein at least one set of the layer-selecting transistors comprises at least one of a floating-gate device, a thin film transistor, and a dielectric-trapped-charge device.

13. The memory device of claim 6, wherein the memory device is a three-dimensional memory device.