Fast filter processor metering and chaining

• US 7,554,984 B2
• Filed: 11/30/2005
• Issued: 06/30/2009
• Est. Priority Date: 11/30/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kalkunte, Mohan, Baden, Eric A.
• Primary Examiner(s): Chan; Wing F
• Assistant Examiner(s): Thompson, Jr.; Otis L
• Application Number:
  US11/289,371
• Publication Number:
  US 20060114900A1
• Time in Patent Office: 1,308 Days
• Field of Search: 370/392
• US Class Current: 370/392
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

A network device for processing packets. The network device includes applying specific fields from a packet to an associated memory device and comparing means for comparing input to the memory device with entries in the memory device. The network device also includes enabling means for enabling selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device. The network device further includes outputting means for outputting an address for a matched entry by the memory device and applying means for applying a match from the memory device to an associated entry in a table for applying actions from the table that are associated with the match to the packet.

Claims

1. A network device for routing packets, the network device comprising:

a processor comprising a plurality of slices for classifying packets and for causing the network device to perform at least one action based on a classification of a packet,

wherein each of the plurality of slices applies specific fields from the packet to an associated memory device that compares input to the memory device with entries in the memory device and outputs an address for a matched entry and wherein the memory device comprises a mask for each memory entry to enable selection of bits that are required to match exactly with bits from the input to the memory device,

wherein each of the plurality of slices applies a match from the memory device to an associated entry in a table to apply actions associated with the packet, and

wherein the memory device comprises a storing unit for storing groups of parsed fields in a predefined number of sections in each entry, wherein if a specific field in one of the predefined number of sections is selected, an extra mask is applied to the memory device.

2. The network device according to claim 1, wherein the network device is configured to parse an incoming packet on at least one of a standard field, a user defined field and another field that does not come from the packet, wherein the user defined field comprises contiguous bytes from predefined bytes in the incoming packet.

3. The network device according to claim 2, wherein the processor is configured to include up to 16 slices, wherein each slice is configured as an independent searching mechanism that is capable of performing independent action.

4. The network device according to claim 1, wherein the memory device is configured to prioritize multiple matches based on an address of each match.

5. The network device according to claim 1, wherein the memory device is configured to assign a highest priority to a match with a lowest physical address.

6. The network device according to claim 1, wherein the processor is configured to provide an address view unit for enabling software associated with the network device to access an entry in the memory device with a predefined key.

7. The network device according to claim 1, wherein the table comprises a storing unit for storing actions associated with the match and wherein the table comprises one entry that corresponds to an entry in the memory device.

8. The network device according to claim 1, wherein the table further comprises storage of four types of action, wherein based on associated action bits, the network device is configured to perform one of drop, replace, redirect or copy packet information.

9. The network device according to claim 1, wherein each of the plurality of slices further comprises at least one field selector for selecting fields that are applied to the memory device.

10. The network device according to claim 1, wherein each of the plurality of slices comprises at least one meter for monitoring packets, wherein bits associated with the meter are provided in the table.

11. The network device according to claim 1, wherein each of the plurality of slices comprises at least one counter.

12. The network device according to claim 1, wherein the processor comprises at least one range checking mechanism that comprises a range table for defining a range within which a value of a selected port must fall.

13. The network device according to claim 12, wherein the processor is configured to apply results from the at least one range checking mechanism as input to the memory device.

14. A network device for routing packets, the network device comprising:

a processor comprising a plurality of slices for classifying packets and for causing the network device to perform at least one action based on a classification of a packet,

wherein each of the plurality of slices applies specific fields from the packet to an associated memory device that compares input to the memory device with entries in the memory device and outputs an address for a matched entry and wherein the memory device comprises a mask for each memory entry to enable selection of bits that are required to match exactly with bits from the input to the memory device, and

wherein each of the plurality of slices applies a match from the memory device to an associated entry in a table to apply actions associated with the packet; and

a chaining mechanism for doubling an amount of data that is used to determine a full match in the memory device, wherein the chaining mechanism is implemented when there is a match in two of the plurality of slices.

15. The network device according to claim 14, wherein the table comprises a setting unit for setting at least two entries to implement the chaining mechanism.

16. The network device according to claim 14, wherein the processor is configured to implement the chaining mechanism in an even memory device entry and an odd memory device entry, when the even and odd memory device entries match their associated inputs and associated chain bits are set.

17. A method for processing packets, the method comprising the steps of:

applying specific fields from a packet to an associated memory device;

comparing input to the memory device with entries in the memory device;

enabling selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device;

outputting an address for a matched entry by the memory device;

applying a match from the memory device to an associated entry in a table;

causing performance of at least one action from the table that is associated with the match to the packet; and

applying a chaining mechanism for doubling an amount of data that is used to determine a full match in the memory device, wherein the chaining mechanism is implemented when there are two matches.

18. The method according to claim 17, further comprising applying results from at least one range checking mechanism as input to the memory device.

19. An apparatus for processing packets, the apparatus comprising:

applying means for applying specific fields from a packet to an associated memory device;

comparing means for comparing input to the memory device with entries in the memory device;

enabling means for enabling selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device;

outputting means for outputting an address for a matched entry by the memory device;

applying means for applying a match from the memory device to an associated entry in a table;

applying means for applying actions from the table that are associated with the match to the packet; and

applying means for applying a chaining mechanism for doubling an amount of data that is used to determine a full match in the memory device, wherein the chaining mechanism is implemented when there are two matches.