Processing apparatus with burst read write operations
First Claim
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1. A digital signal processing system comprising a programmable processor and a peripheral device coupled to the programmable processor, wherein the processor is arranged to communicate with the peripheral device using a read operation and a write operation, respectively, on a single data element, comprising a burst generation device arranged to group a plurality of read operations or a plurality of write operations in a single burst read operation or a single burst write operation, respectively, the burst generation device comprising:
- a collector circuit arranged to receive the read and write operations from the programmable processor, and to generate dedicated tokens, based on information derived from the read and write operations, triggering a release of the single burst read operation or the single burst write operation, respectively;
a first FIFO buffer for storing the dedicated tokens;
a second FIFO buffer for storing information derived from the read and write operations, respectively; and
a release circuit arranged to initiate the release of the single burst write operation or the single burst read operation, respectively, from the second FIFO buffer, under the control of a dedicated token received from the first FIFO buffer.
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Abstract
A digital signal processing system comprises a programmable processor (PROC) and a peripheral device (PD, MEM) coupled to the programmable processor via a burst generation device (BG). The processor is arranged to communicate with the peripheral device using a read operation and a write operation, respectively, on a single data element. The burst generation device (BG) groups a plurality of read operations or a plurality of write operations in a single burst read operation or a single burst write operation, respectively.
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Citations
13 Claims
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1. A digital signal processing system comprising a programmable processor and a peripheral device coupled to the programmable processor, wherein the processor is arranged to communicate with the peripheral device using a read operation and a write operation, respectively, on a single data element, comprising a burst generation device arranged to group a plurality of read operations or a plurality of write operations in a single burst read operation or a single burst write operation, respectively, the burst generation device comprising:
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a collector circuit arranged to receive the read and write operations from the programmable processor, and to generate dedicated tokens, based on information derived from the read and write operations, triggering a release of the single burst read operation or the single burst write operation, respectively; a first FIFO buffer for storing the dedicated tokens; a second FIFO buffer for storing information derived from the read and write operations, respectively; and a release circuit arranged to initiate the release of the single burst write operation or the single burst read operation, respectively, from the second FIFO buffer, under the control of a dedicated token received from the first FIFO buffer. - View Dependent Claims (3, 4, 5, 12, 13)
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2. A digital signal processing system comprising a programmable processor and a peripheral device coupled to the programmable processor, wherein the processor is arranged to communicate with the peripheral device using a read operation and a write operation, respectively, on a single data element, comprising a burst generation device arranged to group a plurality of read operations or a plurality of write operations in a single burst read operation or a single burst write operation, respectively, wherein the programmable processor is further arranged to communicate with the peripheral device using a burst read operation or a burst write operation, respectively, and wherein the burst generation device is further arranged to group the burst read operation and a further burst read operation, or at least one read operation, in the single burst read operation, and to group the burst write operation and a further burst write operation, or at least one write operation, in the single burst write operation, respectively, characterized in that the (burst) read or (burst) write operation, respectively, is arranged to comprise the following information:
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an identifier indicating the validity of the (burst) read or (burst) write operation, respectively; an identifier indicating a (burst) read operation or a (burst) write operation, respectively; a memory address where the (burst) read or the (burst) write operation, respectively, refers to; data to be written in the memory, in case of a (burst) write operation; an identifier indicating the start of a (burst) read operation or a (burst) write operation, respectively; and an identifier indicating the size of the (burst) read operation or the (burst) write operation, respectively. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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Specification
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Current AssigneeIntel Corporation
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Original AssigneeSilicon Hive BV (Intel Corporation)
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InventorsLeijten, Jeroen A.
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Primary Examiner(s)Shin; Christopher B
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Application NumberUS11/573,816Publication NumberTime in Patent Office1,419 DaysField of Search710 22- 35, 710/305, 711/5, 711/104, 711/122, 711/133, 711/141, 711154-156US Class Current710/35CPC Class CodesG06F 13/28 using burst mode transfer, ...
