Multi-protocol serial interface system

• US 7,555,589 B2
• Filed: 03/24/2005
• Issued: 06/30/2009
• Est. Priority Date: 04/20/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Hee Bok
• Primary Examiner(s): Dang; Khanh
• Assistant Examiner(s): DALEY, CHRISTOPHER ANTHONY
• Application Number:
  US11/087,837
• Publication Number:
  US 20050235088A1
• Time in Patent Office: 1,559 Days
• Field of Search: 710/305, 710/10, 713/1, 326/38
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-protocol serial interface system comprises a multi-protocol port pin array, a transport protocol change FPGA, a pull-up change FPGA and a memory. The multi-protocol port pin array comprises a plurality of port pins which interface with an external system for exchanging data with the external system. The transport protocol change FPGA determines roles of port pins of the multi-protocol port pin array depending on a variably changed protocol by selecting one of the plurality of programmed transport protocol circuits in response to code data. The pull-up change FPGA regulates pull-up load of the port pins corresponding to the roles of the port pins determined in the transport protocol change FPGA. The memory stores data processed in the transport protocol change FPGA unit and exchanged with the external system.

Claims

1. A multi-protocol serial interface system comprising:

a multi-protocol port pin array comprising a plurality of port pins, wherein roles of the port pins are changed depending on a protocol applied to a system, the plurality of port pins interfacing with an external system for exchanging data with the external system;

a transport protocol change FPGA for determining the roles of the port pins of the multi-protocol port pin array depending on a variably changed transport protocol circuit logic in response to code data programmed in a nonvolatile coding cell, wherein a role of at least one of the port pins determined by the variably changed transport protocol circuit logic is selected from at least three different roles, wherein the transport protocol change FPGA comprises;

a first pull-up switch for selectively supplying a power voltage in response to a pull-up enable signal,

a first pull-up driving unit for driving the power voltage applied from the first pull-up switch,

a data I/O unit for inputting and outputting the code data,

a ferroelectric capacitor unit for storing the code data in the nonvolatile coding cell,

a second pull-down switch for selectively supplying the ground voltage in response to a pull-down enable signal, and

a second pull-down driving unit for driving the ground voltage applied from the second pull-down switch;

a pull-up change FPGA for regulating pull-up load of the port pins corresponding to the roles of the port pins determined in the transport protocol change FPGA; and

a memory for storing data processed in the transport protocol change FPGA unit and exchanged with the external system.

2. The multi-protocol serial interface system according to claim 1, further comprising a CPU for processing data stored in the memory depending on a predetermined process.

3. The multi-protocol serial interface system according to claim 1, wherein the transport protocol change FPGA includes a plurality of coding cells for storing the code data.

4. The multi-protocol serial interface system according to claim 3, wherein the coding cell stores data using a nonvolatile capacitor.

5. The multi-protocol serial interface system according to claim 1, wherein the transport protocol change FPGA is programmed so that two input/output terminals for a power voltage and a ground voltage are fixed as a specific terminal regardless of the change of the protocol.

6. The multi-protocol serial interface system according to claim 1, wherein the pull-up change FPGA comprises:

a plurality of coding cells for storing pull-up load regulating data to regulate pull-up load of the port pins corresponding to the roles of the port pins determined in the transport protocol change FPGA; and

a load unit for regulating pull-up load of the corresponding port pin in response to the pull-up load regulating data.

7. The multi-protocol serial interface system according to claim 6, wherein the coding cell stores data using a nonvolatile capacitor.

8. The multi-protocol serial interface system according to claim 6, wherein the load unit is a MOS transistor for applying the power voltage to the corresponding port pin in response to the pull-up load regulating data.

9. A multi-protocol serial interface system comprising:

a multi-protocol port pin array comprising a plurality of port pins which interface with an external system for exchanging data with the external system;

a transport protocol change FPGA for determining a role of one port pin of the multi-protocol port pin array to exchange data in a USB method or to produce a reset signal in an ISO standard smart card method depending on a variably changed transport protocol circuit logic in response to code data programmed in a nonvolatile coding cell, wherein the role of the one port pin determined by the variably changed transport protocol circuit logic is selected from at least three different roles, wherein the transport protocol change FPGA comprises;

a first pull-up switch for selectively supplying a power voltage in response to a pull-up enable signal,

a first pull-up driving unit for driving the power voltage applied from the first pull-up switch,

a data I/O unit for inputting and outputting the code data,

a ferroelectric capacitor unit for storing the code data in the nonvolatile coding cell,

a second pull-down switch for selectively supplying the ground voltage in response to a pull-down enable signal, and

a second pull-down driving unit for driving the ground voltage applied from the second pull-down switch;

a pull-up change FPGA for regulating pull-up load of the port pins corresponding to the roles of the port pins determined in the transport protocol change FPGA; and

a memory for storing data processed in the transport protocol change FPGA unit and exchanged with the external system.

10. The multi-protocol serial interface system according to claim 9, further comprising a CPU for processing data stored in the memory depending on a predetermined process.

11. The multi-protocol serial interface system according to claim 9, wherein the transport protocol change FPGA includes a plurality of coding cells for storing the code data.