Independent control of core system blocks for power optimization

• US 7,555,664 B2
• Filed: 01/31/2006
• Issued: 06/30/2009
• Est. Priority Date: 01/31/2006
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sullam, Bert
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US11/343,841
• Publication Number:
  US 20070180279A1
• Time in Patent Office: 1,246 Days
• Field of Search: 713300-340
• US Class Current: 713/324
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence

Abstract

Power management commands are provided to a power management unit of a processing device, wherein the power management unit coupled to a core system block of the processing device. Sampling of the core system block is performed in response to the power management commands by the power management unit, wherein sampling includes periodically powering the core system block.

Claims

1. A method, comprising:

providing power management commands to a power management unit of a processing device, wherein the power management unit is coupled to a core system block of the processing device, wherein the power management commands are provided to the power management unit under control of a processor of the processing device; and

sampling the core system block under control of the power management unit and in response to the power management commands, wherein sampling includes periodically powering the core system block while the processor is in a sleep mode.

2. The method of claim 1 wherein the core system block includes a power supply monitor, wherein sampling includes periodically powering the power supply monitor to monitor an output power of a power supply coupled to the power supply monitor.

3. The method of claim 1 wherein the core system block includes a voltage reference, wherein sampling includes periodically powering the voltage reference.

4. The method of claim 3 wherein the voltage reference is coupled to a sampling switch, the sampling switch to allow a voltage reference output to pass to a consumer circuit during a sampling instance.

5. The method of claim 1 wherein the power management commands are provided to the power management unit via a power management register coupled to the power management unit.

6. The method of claim 5, further comprising:

executing instructions by a processor of the processing device, wherein the instructions initiate the loading of the power management register with values associated with the power management commands.

7. The method of claim 6, further comprising:

defining the power management commands in the instructions; and

storing the instructions in a storage unit of the processing device.

8. The method of claim 1 wherein sampling occurs while a processor of the processing device is in a sleep mode.

9. An article of manufacture, comprising:

a computer-readable storage medium including instructions that, if executed, cause operations comprising;

providing power management commands to a power management unit of a processing device under control of a processor of the processing device, wherein the power management unit is coupled to a core system block of the processing device,

wherein the power management unit is responsive to the power management commands to control sampling of the core system block, wherein sampling includes periodically powering the core system block while the processor is in a sleep mode.

10. The article of manufacture of claim 9 wherein the core system block includes a power supply monitor, wherein sampling includes periodically powering the power supply monitor to monitor an output power of a power supply coupled to the power supply monitor.

11. The article of manufacture of claim 9 wherein the core system block includes a voltage reference, wherein sampling includes periodically powering the voltage reference.

12. The article of manufacture of claim 11 wherein providing the power management commands includes loading a power management register coupled to the power management unit with values associated with the power management commands.

13. The article of manufacture of claim 9 wherein the instructions are part of an application code stored in the processing device.

14. A processing device, comprising:

a core system block;

a power management unit coupled to the core system block;

a processor coupled to the power management unit; and

a storage unit coupled to the processor, wherein the storage unit including instructions that, if executed by the processor, will cause the processor to perform operations comprising;

providing power management commands to the power management unit, wherein the power management unit is responsive to the power management commands to perform sampling of the core system block, wherein sampling includes periodically powering the core system block while the processor is in a sleep mode.

15. The processing device of claim 14 wherein the core system block includes a power supply monitor, wherein sampling includes periodically powering the power supply monitor to monitor an output power of a power supply coupled to the power supply monitor.

16. The processing device of claim 14 wherein the core system block includes a voltage reference, wherein sampling includes periodically powering the voltage reference.

17. The processing device of claim 16 wherein the voltage reference is coupled to a sampling switch, the sampling switch to allow a voltage reference output to pass to a consumer circuit during a sampling instance.

18. The processing device of claim 14, further comprising a power management register coupled between the processor and the power management unit, wherein providing the power management commands includes loading the power management register with values associated with the power management commands.

19. The processing device of claim 14, further comprising a second core system block, wherein sampling of the second core system block is independent of the sampling of the core system block.

20. The processing device of claim 14 wherein the instructions are part of an application code stored in the storage unit.