Timing vector program mechanism
First Claim
1. A system comprising:
- firmware configured to generate timing vectors, each timing vector including a time reference when an operation associated with the timing vector is to be executed;
a processor configured to execute the firmware;
a state machine configured to determine a current time of the system, wherein the state machine is configured to determine a matching time vector of a timing vector based on a comparison of the time reference of the timing vector to the current time; and
operation execution hardware configured to execute the operation associated with the matching timing vector.
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Accused Products
Abstract
Timing vectors are used to pass execution of time-dependent operations from firmware/software to a hardware component (e.g., a state machine). These vectors may be stored as a vector table in a data memory that is accessible by both the firmware/software and the hardware component. Based on the processing being performed in the system, the firmware/software will determine that one or more operations are to be performed at a certain time. The firmware/software stores a reference to that time and the operation(s) in a vector. The hardware component monitors time in the system and the vectors to determine whether the current time matches the time associated with a given vector. When there is a match, the hardware component causes the operation(s) associated with the vector to be performed. The system also may perform different operations at a given time depending on the operating condition (e.g., state) of the system.
14 Citations
37 Claims
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1. A system comprising:
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firmware configured to generate timing vectors, each timing vector including a time reference when an operation associated with the timing vector is to be executed; a processor configured to execute the firmware; a state machine configured to determine a current time of the system, wherein the state machine is configured to determine a matching time vector of a timing vector based on a comparison of the time reference of the timing vector to the current time; and operation execution hardware configured to execute the operation associated with the matching timing vector. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of controlling execution of a plurality of operations in a system, the method comprising:
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defining a time reference associated with each one if the operations to be performed; defining, with a CPU, a timing vector corresponding to each time reference and the operation associated with the time reference; determining, with a state machine, a current time of the system; comparing, with the state machine, the current time to the time reference associated with each timing vector to identify matching timing vectors; and when a matching timing vector is identified, executing the operation associated With the matching timing vector. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A tranceiver configures to receive and transmit wireless signals, the tranceiver comprising:
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a register comfigured to store the timing vectors, each timing vector including a time reference and one or more operations to be performed when the time reference equals a system time of the tranceiver; firmware configured to generate the timing vectors, each timing vector including a time reference for when an operation associated with the timing vector is to be executed; a processor configured to execute the firmware; a timing circuitry configured to generate timing information of the tranceiver, including the system time; a state machine configures to compare the system time to the time reference from each of the one or more timing vectors to determine a matching timing vector and perform the one or more operations of the matching timing vector, wherein the one or more operations of the matching vector cannot be performed during a receipt or Transmission of the one or more wireless signals. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37)
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Specification