Data transmitting apparatus, data receiving apparatus, data transmitting method, and data receiving method

• US 7,555,695 B2
• Filed: 10/25/2004
• Issued: 06/30/2009
• Est. Priority Date: 06/09/2004
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Oogami, Syougo, Murakami, Hiroshi
• Primary Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US10/971,099
• Publication Number:
  US 20050278602A1
• Time in Patent Office: 1,709 Days
• Field of Search: 714/757, 714/772, 714/775, 714/789, 714/798, 714/758, 714/776
• US Class Current: 714/758
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0061 Error detection codes

Abstract

A data transmitting apparatus that transmits a plurality of bits in parallel in synchronization with clocks includes a code generating unit that divides transmission data into a plurality of partial data, and generates an error correction code for each of the partial data; a data dividing unit that divides the transmission data into a plurality of 1-clock data formed of a plurality of bits transmitted in parallel; and a transmission control unit that sequentially transmits each of the 1-clock data in synchronization with a clock cycle, and collectively transmits the error correction codes generated by the code generating unit in a 1-clock cycle.

Claims

1. A data transmitting apparatus that transmits a plurality of bits in parallel in a clock cycle, the data transmitting apparatus comprising:

a code generating unit that divides original transmission data into a plurality of partial data, and generates an error correction code for each of the partial data;

a data dividing unit that divides the original transmission data into a plurality of 1-clock data each of which is transmitted in parallel in a clock cycle, wherein the 1-clock data and the partial data are different data; and

a transmission control unit that sequentially transmits the plurality of 1-clock data one-by-one in synchronization with a clock, and collectively transmits the error correction codes generated by the code generating unit in a clock cycle in synchronization with the clock, wherein each of the error correction codes is made redundant if a sum of lengths of the error correction codes is shorter than a size of the 1-clock data.

2. The data transmitting apparatus according to claim 1, wherein the code generating unit divides the original transmission data based on a bit position at which the original transmission data transmitted in a plurality of clock cycles is transmitted in parallel in each of the clock cycles.

3. The data transmitting apparatus according to claim 1, wherein

the code generating unit divides the original transmission data into the plurality of partial data by dividing each of the 1-clock data into a plurality of 1-clock partial data and selecting 1-clock partial data having a different bit position when the 1-clock data is transmitted in parallel from each of the 1-clock data, and

the transmission control unit transmits the error correction code at a bit position different from that of the 1-clock partial data used for generating the error correction code.

4. The data transmitting apparatus according to claim 1, wherein the transmission control unit collectively transmits the error correction codes in a clock cycle after a transmission clock cycle of the 1-clock data.

5. The data transmitting apparatus according to claim 1, wherein the transmission control unit collectively transmits the error correction codes in a clock cycle before a transmission clock cycle of the 1-clock data.

6. The data transmitting apparatus according to claim 1, wherein the transmission control unit includes

a determining unit that determines whether the error correction codes are transmitted after a transmission clock cycle of the 1-clock data;

and

a code transmission unit that collectively transmits the error correction codes when the determining unit determines to transmit the error correction codes.

7. The data transmitting apparatus according to claim 6, wherein the transmission control unit further includes a path monitoring unit that monitors an idle cycle on a data transmission path, wherein

when the determining unit determines not to transmit the error correction codes, the code transmission unit collectively transmits the error correction codes when the path monitoring unit detects the idle cycle on the data transmission path within a predetermined period from transmission of the original transmission data.

8. A data transmitting apparatus that transmits a plurality of bits in parallel in a clock cycle, the data transmitting apparatus comprising:

a code generating unit that divides original transmission data into a plurality of partial data, and generates an error correction code for each of the partial data;

a data dividing unit that divides the original transmission data into a plurality of 1-clock data each of which is transmitted in parallel in a clock cycle, wherein the 1-clock data and the partial data are different data; and

a transmission control unit that sequentially transmits the plurality of 1-clock data one by one in synchronization with a clock, and collectively transmits the error correction codes generated by the code generating unit using an idle cycle of a control signal.

9. A data receiving apparatus that receives a plurality of bits transmitted in parallel in a clock cycle from a data transmitting apparatus, as a 1-clock data, the data receiving apparatus comprising:

a reception control unit that receives transmission data as a plurality of 1-clock data sequentially transmitted by the data transmitting apparatus one-by-one in synchronization with a clock, and collectively receives, in a clock cycle in synchronization with the clock, a plurality of error correction codes generated from a plurality of partial data generated by dividing the transmission data, wherein the 1-clock data and the partial data are different data and each of the error correction codes is made redundant if a sum of lengths of the error correction codes is shorter than a size of the 1-clock data;

a data building unit that builds data from the plurality of 1-clock data received by the reception control unit; and

an error correcting unit that corrects the data built by the data building unit using the error correction codes received by the reception control unit to obtain reception data.

10. The data receiving apparatus according to claim 9, wherein the partial data are generated based on a bit position at which the transmission data, transmitted in a plurality of clock cycles, is transmitted in parallel in each of the clock cycles.

11. The data receiving apparatus according to claim 9, wherein the partial data is the 1-clock data.

12. The data receiving apparatus according to claim 9, wherein the partial data is generated by dividing each of the 1-clock data into a plurality of 1-clock partial data and selecting the 1-clock partial data having a different bit position when the 1-clock partial data is transmitted in parallel from each of the 1-clock data.

13. The data receiving apparatus according to claim 9, wherein the reception control unit collectively receives the error correction codes in a clock cycle after a reception clock cycle of the 1-clock data.

14. The data receiving apparatus according to claim 9, wherein the reception control unit collectively receives the error correction codes in a clock cycle before a reception clock cycle of the 1-clock data.

15. The data receiving apparatus according to claim 9, wherein the reception control unit includes

a determining unit that determines whether the error correction codes are received after a reception clock cycle of the 1-clock data;

and

a code reception unit that collectively receives the error correction codes when the determining unit determines to receive the error correction codes.

16. The data receiving apparatus according to claim 15, wherein the reception control unit further includes a path monitoring unit that monitors an idle cycle on a data transmission path, and

wherein when the determining unit determines not to receive the error correction codes, the code reception unit collectively receives the error correction codes when the path monitoring unit detects the idle cycle on the data transmission path within a predetermined period from reception of the transmission data.

17. A data receiving apparatus that receives a plurality of bits transmitted in parallel in a clock cycle from a data transmitting apparatus, as 1-clock data, the data receiving apparatus comprising:

a reception control unit that receives transmission data as a plurality of 1-clock data sequentially transmitted by the data transmitting apparatus one-by-one in synchronization with a clock, and collectively receives, in a clock cycle in synchronization with the clock, a plurality of error correction codes generated from a plurality of partial data generated by dividing the transmission data using an idle cycle of a control signal, wherein the 1-clock data and the partial data are different data;

a data building unit that builds data from the plurality of 1-clock data received by the reception control unit; and

an error correcting unit that corrects the data built by the data building unit using the error correction codes received by the reception control unit to obtain reception data.

18. A method of transmitting a plurality of bits in parallel in a clock cycle, the method comprising:

dividing original transmission data into a plurality of partial data;

generating an error correction code for each of the partial data;

dividing the original transmission data into a plurality of 1-clock data each of which is transmitted in parallel, wherein the 1-clock data and the partial data are different data;

transmitting sequentially the plurality of 1-clock data one-by-one in synchronization with a clock; and

transmitting the error correction codes generated by the code generating unit in a clock cycle collectively in synchronization with the clock, wherein each of the error correction codes is made redundant if a sum of lengths of the error correction codes is shorter than a size of the 1-clock data.

19. A method of receiving a plurality of bits transmitted in parallel in a clock cycle from a data transmitting apparatus, as a 1-clock data, the method comprising:

receiving a transmission data as a plurality of 1-clock data sequentially transmitted by the data transmitting apparatus one-by-one in synchronization with a clock;

receiving, in a clock cycle in synchronization with the clock, a plurality of error correction codes generated from a plurality of partial data generated by dividing the transmission data collectively, wherein the 1-clock data and the partial data are different data and each of the error correction codes is made redundant if a sum of lengths of the error correction codes is shorter than a size of the 1-clock data;

building data from the plurality of 1-clock data received; and

correcting the data built at the building using the error correction codes received to obtain a reception data.