IC intrusion detection

• US 7,555,787 B2
• Filed: 02/09/2005
• Issued: 06/30/2009
• Est. Priority Date: 02/24/2004
• Status: Active Grant

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Clercq, Mark Nadim Olivier
• Primary Examiner(s): Chai; Longbit
• Application Number:
  US10/590,388
• Publication Number:
  US 20080260150A1
• Time in Patent Office: 1,602 Days
• Field of Search: 726/34
• US Class Current: 726/34
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: H04L 2209/08 Randomization, e.g. dummy operations or using noise
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]

Abstract

The invention relates to an electronic device for cryptographic processing, having at least two electronic circuits (IC, CC, CP) coupled via a connection means, wherein the connection means is arranged for transferring data signals between the two electronic circuits. The electronic device further has a monitoring circuit (401) arranged to monitor a deviation in the capacitance of the connection means. In case the deviation exceeds a predetermined value an alert signal (411) is generated.

Claims

1. An electronic device for cryptographic processing, comprising

at least two electronic circuits coupled via a connection means, wherein the connection means comprises a bus having a plurality of address bit lines and a plurality of data bit lines arranged for transferring data signals between the two electronic circuits, wherein the data signals convey protected information, and

a monitoring circuit arranged to monitor a deviation in the capacitance of the connection means and to generate an alert signal if the deviation exceeds a predetermined value, wherein the monitoring circuit is further configured to generate a plurality of alert signals, including up to one alert signal for each address bit line and data bit line that is monitored, wherein the monitoring circuit further comprises logic gates to combine the plurality of alert signals into a single alert signal and to output the single alert signal.

2. An electronic device for cryptographic processing according to claim 1, wherein the monitoring circuit is arranged to monitor the data signals transferred via the connection means and to compare a monitored signal with a reference signal.

3. An electronic device according to claim 2, wherein the monitoring circuit is a propagation delay detection circuit.

4. An electronic device according to claim 3, wherein the propagation delay detection circuit is configured to:

perform a comparison of a plurality of signal values of the monitored signal with a plurality of signal values of the reference signal, and

detect a propagation delay between the monitored signal and the reference signal based on the comparison of the signal values of the monitored signal and the reference signal.

5. An electronic device according to claim 2, wherein the monitoring circuit is a slew-rate deviation detection circuit.

6. An electronic device according to claim 5, wherein the slew-rate deviation detection circuit is configured to:

perform a comparison of a plurality of signal values of the monitored signal with a plurality of signal values of the reference signal, and

detect a slew-rate deviation between the monitored signal and the reference signal based on the comparison of the signal values of the monitored signal and the reference signal.

7. An electronic device according to claim 2, wherein the reference signal is derived from a Monte-Carlo analysis performed on the electronic device.

8. An electronic device according to claim 2, wherein the electronic device further comprises a dummy electronic circuit having at least a dummy connection means with a capacitance comparable to that of the connection means, and wherein the monitoring circuit is further arranged to determine the reference signal by monitoring the dummy connection means when transferring a data signal identical to that transferred via the connection means.

9. An electronic device according to claim 1, wherein the electronic circuits comprise a logical circuit and a storage element arranged to store data output by the logical circuit.

10. An electronic device according to claim 1, wherein the monitoring circuit is arranged to monitor a value of the capacitance of the connection means and to compare the monitored value with a reference value.

11. An electronic device according to claim 1, wherein the electronic device is further arranged to use the alert signal to power down at least a part of the electronic device.

12. An electronic device according to claim 1, wherein the monitoring circuit is further configured to generate the alert signal in response to detection of a probe electrically coupled to the connection means, wherein the probe is electrically coupled to the connection means to gain unauthorized access to the protected information conveyed by the data signals.

13. An electronic device according to claim 1, wherein the monitoring circuit is further configured to monitor the deviation in the capacitance of the connection means by monitoring two or more properties related to the capacitance of the connection means, wherein the properties related to the capacitance of the connections means comprise capacitance, propagation delay, and slew-rate deviation.

14. An electronic device according to claim 1, wherein the monitoring circuit is further configured to monitor all of the address and data bit lines of the bus.

15. A method for cryptographic processing, using an electronic device comprising at least two electronic circuits coupled via a connection means, comprising

transferring data signals between the two electronic circuits via the connection means comprising a bus having a plurality of address bit lines and a plurality of data bit lines, wherein the data signals convey protected information,

monitoring a deviation in the capacitance of the connection means,

generating a plurality of alert signals, including up to one alert signal for each address bit line and data bit line that is monitored, if the deviation exceeds a predetermined value, and

combining the plurality of alert signals through logic gates into a single alert signal to output the single alert signal.

16. A method according to claim 15, wherein monitoring the deviation in the capacitance of the connection means further comprises monitoring a propagation delay between the monitored signal and a reference signal, the method further comprising:

performing a comparison of a plurality of signal values of the monitored signal with a plurality of signal values of the reference signal, and

detecting a propagation delay between the monitored signal and the reference signal based on the comparison of the signal values of the monitored signal and the reference signal.

17. A method according to claim 15, wherein monitoring the deviation in the capacitance of the connection means further comprises monitoring a slew-rate deviation between the monitored signal and a reference signal, the method further comprising:

performing a comparison of a plurality of signal values of the monitored signal with a plurality of signal values of the reference signal, and

detecting a slew-rate deviation between the monitored signal and the reference signal based on the comparison of the signal values of the monitored signal and the reference signal.

18. A method according to claim 15, wherein monitoring the deviation in the capacitance of the connection means further comprises:

directly monitoring a capacitance of the connection means, and

comparing the capacitance of the connection means to a threshold.