High-density nonvolatile memory

• US 7,557,405 B2
• Filed: 04/10/2006
• Issued: 07/07/2009
• Est. Priority Date: 12/19/2002
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Mahajani, Maitreyee, Herner, S. Brad
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US11/401,073
• Publication Number:
  US 20060189077A1
• Time in Patent Office: 1,184 Days
• Field of Search: 257/296, 257208-209, 257314-318, 438257-258
• US Class Current: 257/318
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 27/148 Charge coupled imagers individual charge coupled devices H01L29/765
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

An improved nonvolatile memory cell made by a method for fabricating a three dimensional monolithic memory with increased density. The memory cell includes at least a part of a first conductor, a semiconductor element, and at least a part of a second conductor. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements, preferably comprising two diode portions, optionally forming an antifuse above or below both of the diode portions, and then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

Claims

1. A nonvolatile memory cell comprising:

at least a portion of a first conductor at a first height above a substrate and extending in a first direction;

a first polycrystalline semiconductor element above the first conductor, wherein the semiconductor element comprises a heavily doped P-type region and a heavily doped N-type region, without an antifuse layer between the heavily doped P-type region and the heavily doped N-type region; and

at least a portion of a second conductor above the semiconductor element and extending in a second direction, the second direction substantially different from the first direction.

2. The nonvolatile memory cell of claim 1 wherein the semiconductor element is a vertically oriented pillar.

3. The nonvolatile memory cell of claim 1 wherein the heavily doped P-type region is above the heavily doped N-type region.

4. The nonvolatile memory cell of claim 1 wherein the heavily doped N-type region is above the heavily doped P-type region.

5. The nonvolatile memory cell of claim 1 wherein a lightly doped region is disposed between the heavily doped N-type region and the heavily doped P-type region.

6. The nonvolatile memory cell of claim 1 wherein the substrate comprises monocrystalline silicon.

7. The nonvolatile memory cell of claim 1 wherein the first conductor or the second conductor comprises tungsten.

8. The nonvolatile memory cell of claim 1 wherein the second direction is substantially perpendicular to the first direction.

9. A nonvolatile memory cell comprising:

at least a portion of a first conductor at a first height above a substrate and extending in a first direction;

a first polycrystalline semiconductor element above the first conductor, wherein the first polycrystalline semiconductor element comprises a heavily doped P-type region and a heavily doped N-type region;

at least a portion of a second conductor above the first polycrystalline semiconductor element and extending in a second direction, the second direction substantially different from the first direction; and

an antifuse layer disposed above the first polycrystalline semiconductor element and below the second conductor and without another antifuse layer between the heavily doped P-type region and the heavily doped N-type region.

10. The nonvolatile memory cell of claim 9 wherein the antifuse layer is an oxide layer.

11. The nonvolatile memory cell of claim 10 wherein the oxide layer comprises silicon dioxide.

12. The nonvolatile memory cell of claim 9 wherein the semiconductor element is a vertically oriented pillar.

13. The nonvolatile memory cell of claim 9 wherein the heavily doped P-type region is above the heavily doped N-type region.

14. The nonvolatile memory cell of claim 9 wherein the heavily doped N-type region is above the heavily doped P-type region.

15. The nonvolatile memory cell of claim 9 wherein a lightly doped region is disposed between the heavily doped N-type region and the heavily doped P-type region.

16. The nonvolatile memory cell of claim 9 wherein the substrate comprises monocrystalline silicon.

17. The nonvolatile memory cell of claim 9 wherein the first conductor or the second conductor comprises tungsten.

18. The nonvolatile memory cell of claim 9 wherein the second direction is substantially perpendicular to the first direction.

19. A nonvolatile memory cell comprising:

at least a portion of a first conductor at a first height above a substrate and extending in a first direction;

a first polycrystalline semiconductor element above the first conductor, wherein the first polycrystalline semiconductor element comprises a heavily doped P-type region and a heavily doped N-type region;

at least a portion of a second conductor above the first polycrystalline semiconductor element and extending in a second direction, the second direction substantially different from the first direction; and

an antifuse layer disposed above the first conductor and below the first polycrystalline semiconductor element and without another antifuse layer between the heavily doped P-type region and the heavily doped N-type region.

20. The nonvolatile memory cell of claim 19 wherein the antifuse layer is an oxide layer.

21. The nonvolatile memory cell of claim 19 wherein the oxide layer comprises silicon dioxide.

22. The nonvolatile memory cell of claim 19 wherein the semiconductor element is a vertically oriented pillar.

23. The nonvolatile memory cell of claim 19 wherein the heavily doped P-type region is above the heavily doped N-type region.

24. The nonvolatile memory cell of claim 19 wherein the heavily doped N-type region is above the heavily doped P-type region.

25. The nonvolatile memory cell of claim 19 wherein a lightly doped region is disposed between the heavily doped N-type region and the heavily doped P-type region.

26. The nonvolatile memory cell of claim 19 wherein the substrate comprises monocrystalline silicon.

27. The nonvolatile memory cell of claim 19 wherein the first conductor or the second conductor comprises tungsten.

28. The nonvolatile memory cell of claim 19 wherein the second direction is substantially perpendicular to the first direction.