Segmented pillar layout for a high-voltage vertical transistor

• US 7,557,406 B2
• Filed: 02/16/2007
• Issued: 07/07/2009
• Est. Priority Date: 02/16/2007
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Parthasarathy, Vijay, Grabowski, Wayne Bryan
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): SHOOK, DANIEL P
• Application Number:
  US11/707,406
• Publication Number:
  US 20080197417A1
• Time in Patent Office: 872 Days
• Field of Search: 438/138, 438/270, 438/271, 438/272, 438268- 72, 257/331, 257/E21.418, 257/E27.06, 257/E27.081, 257/327
• US Class Current: 257/327
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.

Claims

1. An apparatus comprising:

a plurality of transistor segments arranged on a die, each transistor segment having a racetrack shape with a length elongated in a first lateral direction and a width in a second lateral direction, each transistor segment including;

a pillar of a semiconductor material, the pillar including an extended drain region that extends in a vertical direction through the die;

a first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions;

wherein the transistor segments are arranged into a plurality of sections, a first section comprising a first row of transistor segments arranged in a side-by-side relationship in the second lateral direction, and a second section comprising a second row of transistor segments arranged in the side-by-side relationship in the second lateral direction, the second dielectric region of each transistor segment of the first section being merged with the second dielectric region of each transistor segment of the second section.

2. The apparatus of claim 1 wherein the transistor segments of the first and second sections are each separated in the first lateral direction by at least one dummy pillar of the semiconductor material.

3. The apparatus of claim 2 wherein the at least one dummy pillar comprises a single dummy pillar that separates the first and second sections.

4. The apparatus of claim 3 wherein the single dummy pillar adjoins, in the first lateral direction, a rounded end of the second dielectric region of each transistor segment of the first and second sections.

5. The apparatus of claim 1 wherein the second dielectric region is terminated at each end in the first lateral direction in a rounded end.

6. The apparatus of claim 1 wherein the first and second field plates are fully insulated from the extended drain region, the first field plate being laterally surrounded by the pillar, and the second field plate laterally surrounding the pillar.

7. An apparatus comprising:

a plurality of transistor segments arranged on a die, each transistor segment having a racetrack shape with a length elongated in a first lateral direction and a width in a second lateral direction, each transistor segment including;

a pillar of a semiconductor material, the pillar including an extended drain region that extends in a vertical direction through the die;

a first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions;

wherein the transistor segments are arranged into a plurality of sections, a first section comprising a first row of transistor segments arranged in a side-by-side relationship in the second lateral direction, and a second section comprising a second row of transistor segments arranged in the side-by-side relationship in the second lateral direction, the transistor segments of the first and second sections each being separated in the first lateral direction by a plurality of dummy pillars of the semiconductor material, each dummy pillar being centrally located between rounded ends of first and second adjacent pairs of transistor segments of the first and second sections, respectively.

8. The apparatus of claim 7 wherein the pillar further comprises a source region disposed near a top surface of the die, and a body region that vertically separates the source region from the extended drain region.

9. The apparatus of claim 8 further comprising a gate disposed within the first and second dielectric regions adjacent the body region, the gate being insulated from the body region and the first and second field plates.

10. The apparatus of claim 7 wherein the first and second sections each extend in the second lateral direction substantially across a width of the die, the first section and the second section additively extending in the first lateral direction substantially across a length of the die.

11. A transistor comprising:

a semiconductor die;

a plurality of transistor segments arranged to substantially cover the semiconductor die, each transistor segment having a length that extends in a first lateral direction and a width that extends in a second lateral direction, the length being at least 20 times greater than the width, each transistor segment including;

a pillar of a semiconductor material, the pillar including an extended drain region that extends in a vertical direction through the semiconductor die, the pillar extending in the first and second lateral directions to form a continuous racetrack-shaped ring or oval;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric re ion being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions; and

wherein the transistor segments are arranged into two or more sections located in corresponding areas of the semiconductor die, one or more dummy pillars separating each of the two or more sections, the second dielectric region of each transistor segment of the first section being merged with the second dielectric region of each transistor segment of the second section.

12. The transistor of claim 11 wherein a first section comprises a first row of transistor segments arranged in a side-by-side relationship in the second lateral direction, and a second section comprising a second row of transistor segments arranged in the side-by-side relationship in the second direction.

13. The transistor of claim 12 wherein the second field plates of the transistor segments of the first and second sections are merged along a substantial length in the first lateral direction.

14. The transistor of claim 12 wherein a ratio of the length and the width of the transistor segments in the first and second sections is in a range of about 30 to 80.

15. The transistor of claim 11 wherein the pillar further comprises a source region disposed near a top surface of the semiconductor die, and a body region that vertically separates the source region from the extended drain region.

16. The transistor of claim 15 further comprising a trench gate structure that includes first and second gate members respectively disposed in the first and second dielectric regions near the top of the pillar adjacent the body region.

17. The transistor of claim 11 wherein the transistor segments of a first section are shifted in the first literal direction with respect to the transistor segments of a second section.

18. A transistor fabricated on a semiconductor die, comprising:

a first section of transistor segments disposed in a first area of the semiconductor die;

a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area, each of the transistor segments in the first and second sections including;

a pillar of a semiconductor material that extends in a vertical direction, the pillar having a source region disposed near a top surface of the die, and an extended drain region disposed beneath the source region, the pillar extending in the first and second lateral directions to form a continuous racetrack-shaped ring or oval;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar, the second dielectric region of each transistor segment of the first section being merged with the second dielectric region of each transistor segment of the second section;

first and second field plates respectively disposed in the first and second dielectric regions;

the second field plates of pairs of adjacent transistor segments of the first and second sections being either respectively separated or partially merged; and

wherein the first section comprises a first row of transistor segments arranged in a side-by-side relationship in the second lateral direction, and the second section comprises a second row of transistor segments arranged in the side-by-side relationship in the second direction, the first and second sections being separated in the first lateral direction by a dummy pillar of the semiconductor material.

19. The transistor of claim 18 wherein the transistor segments of a first section are shifted by one-half of the length in the first lateral direction with respect to the transistor segments of a second section.

20. The transistor of claim 19 wherein the second field plates of the transistor segments of the first and second sections are merged along a substantial length in the first lateral direction.

21. The transistor of claim 18 wherein each transistor segment further includes a body region that vertically separates the source and extended drain regions, and a trench gate structure that includes first and second gate members respectively disposed in the first and second dielectric regions near a top of the pillar adjacent the body region.