Arc fault circuit interrupter and method of parallel and series arc fault detection

• US 7,558,033 B2
• Filed: 02/27/2007
• Issued: 07/07/2009
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Eaton Intelligent Power Limited (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Zhou, Xin, Shea, John J., Parker, Kevin L., Engel, Joseph C., Miller, Theodore J.
• Primary Examiner(s): Jackson; Stephen W
• Assistant Examiner(s): Patel; Dharti H
• Application Number:
  US11/679,281
• Publication Number:
  US 20080204949A1
• Time in Patent Office: 861 Days
• Field of Search: None
• US Class Current: 361/42
• CPC Class Codes: H02H 1/0015 Using arc detectors

Abstract

An arc fault circuit interrupter includes separable contacts, a neutral conductor, an operating mechanism structured to open and close the separable contacts, at least one current sensor structured to sense current flowing through the separable contacts and output a sensed current value; and a processor. The processor includes a first routine structured to provide parallel arc fault detection, a second routine structured to provide series arc fault detection, and a third routine structured to enable the first routine and disable the second routine for a predetermined time when the sensed current value is greater than a predetermined value and to enable the second routine and disable the first routine for the predetermined time when the sensed current value is less than the predetermined value.

Claims

1. An arc fault circuit interrupter comprising:

separable contacts;

a neutral conductor;

an operating mechanism structured to open and close said separable contacts;

at least one current sensor structured to sense current flowing through said separable contacts and output a sensed current value; and

a processor comprising a first routine structured to provide parallel arc fault detection, a second routine structured to provide series arc fault detection, and a third routine structured to enable said first routine and disable said second routine when said sensed current value is greater than a predetermined value and to enable said second routine and disable said first routine when said sensed current value is less than said predetermined value, wherein said processor is structured to cooperate with one of said at least one current sensor to determine and store a plurality of peak values of the sensed current value for a plurality of half-cycles of said current flowing through said separable contacts;

wherein said first routine is further structured to determine at least one of;

(a) whether a first predetermined plurality of said half-cycles of said current occur in succession and correspond to a non-unity power factor, and to responsively inhibit said parallel arc fault detection for a first predetermined time, and (b) whether a second predetermined plurality of said half-cycles of said current occur in succession and each of said second predetermined plurality of said half-cycles of said current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of said current of like polarity or of differing polarity, and to responsively inhibit said parallel arc fault detection for a second predetermined time; and

wherein said processor is further structured to determine that said parallel arc fault detection is not inhibited for at least one of said first predetermined time and said second predetermined time, and to responsively indicate that at least one of said half-cycles of said current having a peak amplitude greater than or equal to a predetermined amount is a parallel arc.

2. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to indicate a parallel arc fault in response to a predetermined plurality of occurrences of said parallel arc, said occurrences each being separated from one another by no more than a third predetermined time.

3. The arc fault circuit interrupter of claim 2 wherein said processor is further structured to trip open said separable contacts in response to said indicate a parallel arc fault.

4. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to determine both of said (a) whether a first predetermined plurality of said half-cycles of said current occur in succession and correspond to a non-unity power factor and said (b) whether a second predetermined plurality of said half-cycles of said current occur in succession and each of said second predetermined plurality of said half-cycles of said current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of said current of like polarity or of differing polarity;

and wherein said processor is further structured to determine that said parallel arc fault detection is not inhibited for both of said first predetermined time and said second predetermined time.

5. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to sense a zero crossing of a line-to-neutral voltage between one of said separable contacts and said neutral conductor, and to determine whether said sensed current value corresponds to a non-unity power factor for each of said half-cycles of said current.

6. The arc fault circuit interrupter of claim 1 wherein said predetermined value is 42 A peak.

7. An arc fault circuit interrupter for an alternating current power circuit including a plurality of half-cycles, said arc fault circuit interrupter comprising:

separable contacts;

an operating mechanism structured to open and close said separable contacts;

at least one current sensor structured to sense current flowing through said separable contacts and output a sensed current value;

a processor comprising a first routine structured to provide parallel arc fault detection, a second routine structured to provide series arc fault detection, and a third routine structured to enable said first routine and disable said second routine when said sensed current value is greater than a first predetermined value and to enable said second routine and disable said first routine when said sensed current value is less than said first predetermined value;

a first band pass filter cooperating with one of said at least one current sensor to output a first pass band having a first range of frequencies of said sensed current;

a second band pass filter cooperating with one of said at least one current sensor to output a second pass band having a second range of frequencies of said sensed current, said second range of frequencies not overlapping and being greater than said first range of frequencies;

a first peak detector cooperating with said first band pass filter to detect a plurality of first peak current values from said first pass band;

a second peak detector cooperating with said second band pass filter to detect a plurality of second peak current values from said second pass band;

a first envelope detector cooperating with said first band pass filter to detect a plurality of first occurrences from said first pass band being within a first predetermined range of magnitudes;

a second envelope detector cooperating with said second band pass filter to detect a plurality of second occurrences from said second pass band being within a second predetermined range of magnitudes; and

a counter structured to count said first and second occurrences,

wherein said second routine is further structured to disable said series arc detection when the sensed current is greater than a second predetermined value,

wherein said processor cooperates with said counter to determine a plurality of counts from said counter for said half-cycles,

wherein said processor further cooperates with said first and second peak detectors to determine a plurality of tallies responsive to one of said first peak current values exceeding a first threshold for said half-cycles or one of said second peak current values exceeding a second threshold for said half-cycles,

wherein said processor is structured to determine presence of series arcing in said power circuit from;

(1) said sensed current being less than said second predetermined value for at least a predetermined time, (2) the tally for a current one of said half-cycles being not zero, and (3) the count of said counter for the current one of said half-cycles being different than the count of said counter for an immediately previous one of said half-cycles of like polarity by at least a third predetermined value, and

wherein said processor is further structured to increase a series chaos accumulator responsive to said presence of series arcing.

8. The arc fault circuit interrupter of claim 7 wherein said first and second thresholds are first and second lower thresholds, respectively, both of said first and second lower thresholds being structured to enable said processor to detect noise generated by a series arc fault;

and wherein said processor is further structured to determine said plurality of tallies responsive to said one of said first peak current values exceeding said first lower threshold and being less than a third upper threshold for said half-cycles or said one of said second peak current values exceeding said second lower threshold for said half-cycles.

9. The arc fault circuit interrupter of claim 7 wherein said first and second thresholds are first and second lower thresholds, respectively;

wherein said first band pass filter has an output that is input by said first peak detector;

wherein said second band pass filter has an output that is input by said second peak detector; and

wherein said processor is further structured to remove baseline shifting of the outputs of said peak detectors.

10. The arc fault circuit interrupter of claim 7 wherein the minimum frequency of said first range of frequencies is about 50 kHz;

wherein the maximum frequency of the second range of frequencies is about 2 MHz; and

wherein each of said first and second band pass filters have a center frequency to bandwidth ratio of greater than about 5.

11. The arc fault circuit interrupter of claim 7 wherein said counter structured to count said first and second occurrences is structured to count high frequency pulses for each of said half-cycles to eliminate load noise associated with periodic high frequency signals.

12. The arc fault circuit interrupter of claim 7 wherein said processor is further structured to determine if said series chaos accumulator is negative and to responsively set said series chaos accumulator to zero.

13. The arc fault circuit interrupter of claim 7 wherein said processor comprises an output;

and wherein said processor is further structured to determine the occurrence of a series arc fault when said series chaos accumulator is greater than a fourth predetermined value and to responsively set the output of said processor to cause said operating mechanism trip open said separable contacts.

14. The arc fault circuit interrupter of claim 7 wherein said processor is further structured to increase said series chaos accumulator by a predetermined amount responsive to said presence of series arcing.

15. The arc fault circuit interrupter of claim 7 wherein said processor is further structured to decrease said series chaos accumulator by a predetermined amount when said processor does not determine said presence of series arcing in said power circuit.

16. A method of detecting parallel arc faults or series arc faults for an alternating current power circuit, said method comprising:

sensing current flowing through said alternating current power circuit and outputting a sensed current value;

providing parallel arc fault detection;

providing series arc fault detection;

enabling said parallel arc fault detection and disabling said series arc fault detection for a predetermined time when said sensed current value is greater than a predetermined value;

otherwise, enabling said series arc fault detection and disabling said parallel arc fault detection for a predetermined time when said sensed current value is less than said predetermined value;

sensing a plurality of half-cycles of current flowing in said power circuit;

providing said parallel arc fault detection of said current flowing in said power circuit;

ignoring any of said half-cycles of current having a peak amplitude less than a predetermined amount;

determining at least one of;

(i) whether a first predetermined plurality of said half-cycles of current occur in succession and have non-unity power factor and responsively inhibiting said parallel arc fault detection for a first predetermined time, and

(ii) whether a second predetermined plurality of said half-cycles of current occur in succession and each of said second predetermined plurality of said half-cycles of current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of current of like polarity or of differing polarity, and responsively inhibiting said parallel arc fault detection for a second predetermined time; and

determining whether said ignoring and said determining are not met, and responsively indicating that at least one of said half-cycles of current having a peak amplitude greater than or equal to said predetermined amount is a parallel arc.

17. The method of claim 16 further comprising

counting occurrences of said parallel arc, which are each separated from one another by no more than a third predetermined time;

and

indicating a parallel arc fault in response to a predetermined plurality of said occurrences of said parallel arc, which are each separated from one another by no more than said third predetermined time.

18. The method of claim 16 further comprising

tripping open separable contacts responsive to said indicating a parallel arc fault.

19. The method of claim 16 further comprising

determining both of said (i) whether a first predetermined plurality of said half-cycles of current occur in succession and have non-unity power factor, and said (ii) whether a second predetermined plurality of said half-cycles of current occur in succession and each of said second predetermined plurality of said half-cycles of current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of current of like polarity or of differing polarity.

20. The method of claim 16 further comprising

determining said (i) whether a first predetermined plurality of said half-cycles of current occur in succession and have non-unity power factor, in order to distinguish a motor start inrush current transient from a parallel arc fault.

21. The method of claim 16 further comprising

determining said (ii) whether a second predetermined plurality of said half-cycles of current occur in succession and each of said second predetermined plurality of said half-cycles of current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of current of like polarity or of differing polarity, in order to distinguish an incandescent dimmer inrush current from a parallel arc fault.

22. The method of claim 16 further comprising

employing a voltage having a voltage zero crossing;

and

for each of said half-cycles, determining if said current flowing in said power circuit at the voltage zero crossing has a different polarity than said current flowing in said power circuit about 90 degrees after said voltage zero crossing, and responsively indicating a non-unity power factor.

23. A method of detecting parallel arc faults or series arc faults for an alternating current power circuit, said method comprising:

sensing current flowing through said alternating current power circuit and outputting a sensed current value;

providing parallel arc fault detection;

providing series arc fault detection;

enabling said parallel arc fault detection and disabling said series arc fault detection for a predetermined time when said sensed current value is greater than a predetermined value;

otherwise, enabling said series arc fault detection and disabling said parallel arc fault detection for a predetermined time when said sensed current value is less than said predetermined value;

employing a first band pass filter to output a first pass band having a first range of frequencies of said sensed current value;

employing a second band pass filter to output a second pass band having a second range of frequencies of said sensed current value, said second range of frequencies not overlapping and being greater than said first range of frequencies;

detecting a plurality of first peak current values from said first pass band;

detecting a plurality of second peak current values from said second pass band;

detecting a plurality of first occurrences from said first pass band being within a first predetermined range of magnitudes;

detecting a plurality of second occurrences from said second pass band being within a second predetermined range of magnitudes;

counting said first and second occurrences and outputting a count value;

employing as said predetermined value a first predetermined value;

providing said series arc detection and disabling said series arc detection when said sensed current value is greater than a second predetermined value;

determining a plurality of counts from said count value for said half-cycles;

determining a plurality of tallies responsive to one of said first peak current values exceeding a first threshold for said half-cycles or one of said second peak current values exceeding a second threshold for said half-cycles;

determining presence of series arcing in said power circuit from;

(1) said sensed current value being less than said second predetermined value for at least a first predetermined time, (2) the tally for a current one of said half-cycles being not zero, and (3) the count for the current one of said half-cycles being different than the count for an immediately previous one of said half-cycles of like polarity by at least a third predetermined value; and

increasing a series chaos accumulator responsive to said presence of series arcing.

24. The method of claim 23 further comprising

determining the occurrence of a series arc fault when said series chaos accumulator is greater than a fourth predetermined value and responsively interrupting said current flowing through said power circuit.

25. An arc fault circuit interrupter comprising:

separable contacts;

a neutral conductor;

an operating mechanism structured to open and close said separable contacts;

at least one current sensor structured to sense current flowing through said separable contacts and output a sensed current value; and

a processor comprising a first routine structured to provide parallel arc fault detection, a second routine structured to provide series arc fault detection, and a third routine structured to enable said first routine and disable said second routine when said sensed current value is greater than a predetermined value and to enable said second routine and disable said first routine when said sensed current value is less than said predetermined value, wherein said processor is structured to cooperate with one of said at least one current sensor to determine and store a plurality of peak values of the sensed current value for a plurality of half-cycles of said current flowing through said separable contacts;

wherein said first routine is further structured to determine whether a predetermined plurality of said half-cycles of said current occur in succession and correspond to a non-unity power factor, and to responsively inhibit said parallel arc fault detection for a predetermined time; and

wherein said processor is further structured to determine that said parallel arc fault detection is not inhibited for said predetermined time, and to responsively indicate that at least one of said half-cycles of said current having a peak amplitude greater than or equal to a predetermined amount is a parallel arc.

26. An arc fault circuit interrupter comprising:

separable contacts;

a neutral conductor;

an operating mechanism structured to open and close said separable contacts;

at least one current sensor structured to sense current flowing through said separable contacts and output a sensed current value; and

a processor comprising a first routine structured to provide parallel arc fault detection, a second routine structured to provide series arc fault detection, and a third routine structured to enable said first routine and disable said second routine when said sensed current value is greater than a predetermined value and to enable said second routine and disable said first routine when said sensed current value is less than said predetermined value, wherein said processor is structured to cooperate with one of said at least one current sensor to determine and store a plurality of peak values of the sensed current value for a plurality of half-cycles of said current flowing through said separable contacts;

wherein said first routine is further structured to determine whether a predetermined plurality of said half-cycles of said current occur in succession and each of said predetermined plurality of said half-cycles of said current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of said current of like polarity or of differing polarity, and to responsively inhibit said parallel arc fault detection for a predetermined time; and

wherein said processor is further structured to determine that said parallel arc fault detection is not inhibited for said predetermined time, and to responsively indicate that at least one of said half-cycles of said current having a peak amplitude greater than or equal to a predetermined amount is a parallel arc.