Over current protection circuit and method

• US 7,558,037 B1
• Filed: 04/30/2008
• Issued: 07/07/2009
• Est. Priority Date: 04/30/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: He, Yi, Chan, Tuck Meng, Gong, Xiaowu
• Primary Examiner(s): Jackson; Stephen W
• Assistant Examiner(s): PATEL, DHARTI HARIDAS
• Application Number:
  US12/112,885
• Time in Patent Office: 433 Days
• Field of Search: 361/91.1, 361/18, 361 54- 56, 361 78- 79, 361/86, 361/88, 361/111
• US Class Current: 361/93.1
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/3376 with automatic control of output voltage or current

Abstract

Circuit and method for providing over-current and overloading protection with a single additional pin. A converter controller circuit is provided that includes a voltage controlled oscillator and outputs upper and lower gating signals for driving the upper and lower driving transistors in a voltage converter, for example, in an inductor-inductor capacitor half-bridge circuit topology. A current sense input pin of the circuit receives a voltage corresponding to the current flowing in the half-bridge circuit. A feedback input pin has an external capacitor coupled to it and receives a voltage from an output voltage sensor at the output terminals. Over-current protection is provided by sensing the voltage at the current sense input pin with no external components needed. Overload protection is provided by utilizing the external feedback capacitor and the feedback input pin during overload conditions. Methods for providing over-current and overload protection are disclosed.

Claims

1. An integrated circuit, comprising:

a voltage controlled oscillator for providing pulses at a frequency corresponding to a voltage received at an feedback input pin;

a first switching output for driving a high-side driver transistor at a frequency proportional to the pulses;

a second switching output for driving a low-side driver transistor at a frequency proportional to the pulses, the second switching output being a non-overlapping inverted signal from the first switching output;

a current sense input pin for receiving a voltage corresponding to current flowing in an external load circuit;

a latch off function that outputs a latch off signal when the voltage received at the current sense input pin is greater than a first threshold voltage;

a VCO influence function outputting a VCO influence signal that increases the frequency of the VCO when the voltage input to the current sense input pin is greater than a second threshold voltage, and that decreases the frequency of the VCO when the voltage input to the current sense input pin is less than a third threshold voltage, the second threshold voltage being less than the first threshold voltage and greater than the third threshold voltage; and

a switch off function that outputs a switch off signal when the voltage at the feedback input pin exceeds a maximum operating voltage for a time period greater than a blanking time period.

2. The integrated circuit of claim 1, wherein the VCO influence function further comprises:

a first comparator comparing the voltage at the current sense input pin to the second threshold voltage and outputting a set indicator signal;

a second comparator comparing the voltage at the current sense input in to the third threshold voltage and outputting a reset indicator signal;

a set reset register coupled to the set indicator signal and the reset indicator signal and outputting a registered output signal;

an internal capacitor coupled to a charge/discharge circuit, the charge/discharge circuit receiving the registered output signal;

a counter coupled to the charge/discharge circuit by control circuitry, the control circuitry causing the capacitor to rapidly charge and slowly discharge when the registered output signal is false, and to rapidly discharge and slowly charge when the registered output signal is true, and outputting a clock signal when the capacitor reaches a threshold voltage during the charge and discharge cycles;

an up/down count signal of the counter coupled to count up when the registered output signal is true and to count down when the registered output signal is false; and

a digital to analog converter receiving the output of the counter and outputting the VCO influence signal that varies proportional to the counter output.

3. The integrated circuit of claim 1 wherein the latch off function further comprises:

a comparator receiving the voltage at the current sense input pin and comparing it to the first threshold voltage and outputting a high voltage indicator signal; and

a set reset register that is set by high voltage indicator signal, and outputs the latch off signal.

4. The integrated circuit of claim 1, wherein the switch off function further comprises:

a first blanking time circuit outputting a first blanking time signal when the voltage at the feedback input pin is greater than a fourth threshold voltage for a first blanking time period; and

a second blanking time circuit that starts a second blanking time and outputs the switch off signal when the voltage at the feedback input pin is greater than the fourth threshold voltage for a time period that is longer than the first blanking time added with the second blanking time.

5. The integrated circuit of claim 4, wherein the second blanking time circuit further comprises:

an internal feedback resistor coupled between the feedback input pin and a positive power supply;

an internal pull down transistor coupled between the feedback input pin and a ground reference and having a control gate input; and

a charge/discharge control circuit coupled to compare the voltage at the feedback input pin to the fourth reference voltage and to a fifth reference voltage, the fourth reference voltage being greater than the fifth reference voltage, the charge/discharge control circuit coupled to the control gate input to enable the pull down transistor to discharge an external capacitor when the voltage at the feedback input is greater than the fourth reference voltage, and coupled to the control gate input to enable the internal feedback resistor to charge the external capacitor when the voltage at the feedback input is less than the fifth reference voltage.

6. The integrated circuit of claim 5, wherein the second blanking time circuit further comprises a counter that increases each time the voltage on the feedback input pin exceeds the fourth voltage until the counter reaches a maximum that sets the switch off signal.

7. A circuit, comprising:

an upper driver transistor coupled between a positive power supply and a node and receiving an upper gate control signal;

a lower driver transistor coupled between the node and a ground potential and receiving a lower gate control signal;

a first inductor having an input terminal coupled to the node and having an output terminal;

a second inductor having an input terminal coupled to the first inductor output terminal and having an output terminal, the first inductor being part of a transformer having a second inductor coupled to a voltage output;

a capacitor coupled to the output terminal of the second inductor and coupled to the ground potential, the first inductor, second inductor and capacitor forming an LLC circuit;

a current sense resistor coupled in series with the LLC circuit and outputting a current sense voltage proportional to the current flowing in the LLC circuit; and

a converter integrated circuit, comprising;

an internal voltage controlled oscillator (VCO) and circuits outputting the upper gate control signal at an UPPER output pin and the lower gate control signal at a LOWER output pin, the upper and lower gate control signals being non-overlapping pulses of a frequency determined by the VCO frequency;

an over-current protection coupled to a current sense voltage input pin for receiving the current sense voltage, and outputting a latch off signal when the current sense voltage is greater than a first threshold voltage, and outputting a VCO influence signal to the VCO to change the frequency of the VCO when the voltage at the current sense voltage input pin is above a second threshold voltage that is less than the first threshold voltage, and outputting an opposite VCO influence signal when the voltage at the current sense voltage input pin is below a third threshold voltage that is lower than the second threshold voltage; and

an overload protection function coupled to a feedback voltage input pin outputting a switch off signal when the voltage at the feedback voltage input pin is greater than a fourth threshold voltage for a time period that exceeds the sum of a first and an extended blanking time.

8. The circuit of claim 7, wherein the converter integrated circuit stops supplying the upper and lower gate control circuit signals at the upper and lower output pins when the latch off signal is set.

9. The circuit of claim 7, wherein the converter integrated circuit stops supplying the upper and lower gate control circuit signals at the upper and lower output pins when the switch off signal is set.

10. The circuit of claim 7, wherein the over-current protection function further comprises:

a circuit outputting the latch off signal when a first comparator coupled to the voltage at the current sense voltage input pin determines the voltage exceeds the first threshold voltage; and

a VCO influence circuit that outputs the VCO influence signal to increase the frequency of the VCO when the voltage at the current sense input pin is greater than the second threshold voltage and outputs the VCO influence signal to decrease the frequency of the VCO when the voltage at the current sense input pin is lower than the third threshold voltage.

11. The circuit of claim 10, wherein the VCO influence circuit further comprises:

a first comparator outputting a set signal when the currents sense input pin voltage is greater than the second threshold voltage;

a second comparator outputting a reset signal when the voltage at the current sense input pin is less than the third reference voltage;

a set reset register that is set in response to the set signal and reset in response to the reset signal and having a registered output;

an internal current sense capacitor;

a charge/discharge circuit coupled to charge the internal current sense capacitor rapidly and discharge the internal current sense capacitor slowly when the registered output is reset, and coupled to discharge the internal current sense capacitor rapidly and charge the internal current sense capacitor slowly when the registered output is set;

a counter coupled to count when the internal current sense capacitor is charged and discharged to predetermined levels, the counter having an up/down input that causes the counter to increase when the registered output is set and decrease when the registered output is reset; and

a digital to analog converter (DAC) coupled to the counter and outputting the VCO influence signal that increases when the count increases and decreases when the count decreases.

12. The circuit of claim 7, wherein the overload protection circuit further comprises:

a first blanking time circuit that sets a first time signal when the voltage at the feedback voltage input pin is greater than a fourth threshold voltage for a time exceeding a first blanking time; and

a second blanking time circuit that sets the switch off signal when the voltage at the feedback input pin is greater than the fourth threshold voltage for a time exceeding the sum of the first blanking time and a second blanking time.

13. The circuit of claim 12, wherein the first blanking time circuit will stop if the voltage at the feedback input pin returns to a voltage less than the fourth threshold before the first blanking time elapses.

14. The circuit of claim 13, wherein the second blanking time circuit will stop and reset the first blanking time circuit if the voltage at the feedback input pin returns to a voltage less than the fourth threshold voltage for time that exceeds a blanking time reset delay.

15. The circuit of claim 12, wherein the second blanking time circuit further comprises:

an internal feedback resistor coupled to the feedback input pin and to a positive voltage, a discharge transistor coupled between the feedback input pin and a ground potential, and a control circuit for charging the external feedback capacitor coupled to the feedback input pin to a first upper voltage and discharging the external feedback capacitor coupled to the feedback input pin to a first lower voltage;

an upcounter that is increased each time the external feedback capacitor is charged to the upper level voltage by the charge/discharge circuit, the upcounter setting a register when a maximum count is reached; and

the register outputting the switch off signal when the maximum count is reached.

16. A method, comprising:

providing an upper gate control signal to an upper driving transistor coupled to supply a voltage to a node;

providing a lower gate control signal to a lower driving transistor coupled between the node and a ground reference;

coupling an inductor-inductor capacitor (LLC) circuit to the node and to an output voltage;

providing a circuit supplying the upper and lower gate control signals to the upper and lower driving transistors responsive to the frequency of a voltage controlled oscillator (VCO), the upper and lower gate controls signals being non overlapping periodic signals with a frequency proportional to the VCO frequency;

providing a voltage feedback at a feedback input to the circuit from the voltage output to the circuit, the circuit modifying the frequency of the VCO responsive to the feedback input;

coupling an external feedback capacitor between the feedback input pin and the ground potential;

providing a current sense voltage proportional to the current flowing in the LLC circuit at a current sense input to the circuit;

outputting a latch off signal from an over-current protection function in the circuit when the voltage at the current sense input is greater than a first threshold voltage, and outputting a VCO influence signal for modifying the VCO frequency when the voltage at the current sense input is greater than a second threshold voltage that is less than the first threshold voltage, and outputting the VCO influence signal modifying the VCO frequency when the voltage at the current sense input is less than a third threshold voltage that is less than the second threshold voltage; and

outputting a switch off signal to provide overload protection for the LLC circuit when the voltage at the feedback input is greater than a fourth threshold voltage for a time exceeding a blanking time period.

17. The method of claim 16, wherein outputting a switch off signal to provide overload protection further comprises:

providing a first blanking time circuit that sets a first blanking time register if the voltage at the feedback input to the circuit exceeds the fourth threshold voltage for a time greater than a first blanking time period; and

stopping the blanking time circuit if the voltage at the feedback input pin is greater than the fourth threshold for a time less than the first blanking time period, and then returns to a voltage less than the fourth threshold voltage.

18. The method of claim 17 wherein outputting a switch off signal further comprises:

enabling a second blanking time circuit when the register is set indicating the first blanking time has been exceeded;

charging the external feedback capacitor through an feedback resistor internal to the circuit to a first upper level;

discharging the external feedback capacitor through a discharge transistor internal to the circuit to a first lower level;

increasing a counter each time the external feedback capacitor is charged to the upper level; and

outputting the switch off signal when the count reaches a predetermined maximum count value.

19. The method of claim 18, and further comprising:

determining after the first blanking time has elapsed and before the counter reaches the predetermined maximum count that the voltage at the feedback input to the circuit has returned to a voltage less than the fourth threshold voltage for a time period greater than a blanking time reset delay time; and

resetting the counter and the first blanking time register.

20. The method of claim 17, wherein outputting a VCO influence signal further comprises:

determining when the voltage at the current sense input to the circuit is greater than the second threshold voltage and setting a registered output;

determining when the voltage at the current sense input to the circuit is less than the third threshold voltage and resetting a registered output;

providing an current sense capacitor internal to the circuit;

when the registered output is set, rapidly discharging the current sense capacitor and slowly charging the current sense capacitor;

when the registered output is reset, rapidly charging the current sense capacitor and slowly discharging the current sense capacitor;

clocking an up/down counter;

inputting an up signal to the up/down counter when the registered output is set and a down signal to the up/down counter when the registered output is reset; and

outputting the VCO influence signal that increases as the counter increases and decreases as the counter decreases.

21. The method of claim 17 wherein the first threshold voltage is at least 1.5 Volts.

22. The method of claim 17 wherein the second threshold voltage is at least 0.8 Volts.

23. The method of claim 17 wherein the third threshold voltage is not more than 0.75 Volts.

24. The method of claim 17 wherein the fourth threshold voltage is at least 4.5 Volts.

25. A method of providing overload (OLP) and overcurrent (OCP protection for a half-bridge DC convertor circuit having a DC output, comprising:

providing an inductor-inductor capacitor (LLC) circuit coupled to a node;

providing an upper driver transistor coupling the node to a positive power supply, responsive to a periodic upper gating signal having a duty cycle;

providing a lower driver transistor coupling the node to a ground potential, responsive to a periodic lower gating signal having the duty cycle and being non overlapping with the upper gating signal;

providing an integrated circuit that outputs the upper and lower gating signals of said DC convertor circuit, the integrated circuit receiving only a current sense voltage input and a feedback voltage input as signals necessary for controlling said OLP and OCP protection;

coupling an external feedback capacitor to the feedback voltage input;

coupling a feedback sensor to the feedback voltage input; and

wherein the integrated circuit provides the upper and lower gating signals responsive to the frequency of an on board voltage controlled oscillator (VCO), and the integrated circuit provides over-current protection responsive to a voltage at the current sense voltage input that corresponds to the current flowing in the LLC circuit.

33. The method of claim 25 wherein said feedback sensor provides electrical isolation between said feedback voltage input and a DC output of said DC convertor circuit.

34. The method of claim 25 wherein said feedback sensor is an optocoupler.

26. A method, comprising:

providing an inductor-inductor capacitor (LLC) circuit coupled to a node;

providing an upper driver transistor coupling the node to a positive power supply, responsive to a periodic upper gating signal having a duty cycle;

providing a lower driver transistor coupling the node to a ground potential, responsive to a periodic lower gating signal having the duty cycle and being non overlapping with the upper gating signal;

providing an integrated circuit that outputs the upper and lower gating signals, the integrated circuit having a current sense voltage input and a feedback voltage input;

coupling an external feedback capacitor to the feedback voltage input;

coupling a feedback sensor to the feedback voltage input; and

wherein the integrated circuit provides the upper and lower gating signals responsive to the frequency of an on board voltage controlled oscillator (VCO), and the integrated circuit provides over-current protection responsive to a voltage at the current sense voltage input that corresponds to the current flowing in the LLC circuit, and further comprising;

latching off the upper and lower gating signals to the upper and lower driver transistor when the voltage at the current sense input pin exceeds a first threshold voltage; and

modifying the frequency of the VCO when the voltage input to the current sense voltage input pin is greater than a second threshold voltage that is less than the first threshold voltage, and modifying the frequency of the VCO oppositely when the voltage at the current sense input pin is less than a third threshold voltage that is less than the second threshold voltage.

27. The method of claim 26 wherein the integrated circuit switches off the upper and lower gating signals when the voltage at the feedback voltage input exceeds a fourth threshold voltage for a time that is greater than a blanking time period, indicating an overload at the output.

28. The method of claim 27 wherein the integrated circuit switches off the upper and lower gating signals further comprises:

determining when the voltage at the feedback input pin is greater than the fourth threshold voltage for a period of time greater than a first blanking time period;

setting a registered output at the end of the first blanking time period;

determining when the voltage at the feedback input pin is greater than the fourth threshold voltage for a time period greater than the sum of the first blanking time period and a second blanking time period, the blanking time period; and

switching off the integrated circuit when the blanking time period is exceeded.

29. The method of claim 28, wherein determining when the voltage at the feedback input pin is greater than the fourth threshold voltage for a time period greater than the sum of the first blanking time period and a second blanking time period further comprises:

detecting the registered output is set;

charging the external feedback capacitor coupled to the feedback input pin through an internal feedback resistor to a first upper voltage level;

discharging the external feedback capacitor coupled to the feedback input pin through an internal transistor to a first lower voltage level;

clocking an up counter each time the external capacitor is charged to the first voltage level;

repeating the charging and discharging and clocking steps;

detecting a predetermined maximum count in the upcounter; and

setting a switch off signal when the maximum count is reached.

30. The method of claim 29 and further comprising:

after the first blanking time has elapsed and prior to the maximum count being detected, determining that the voltage at the feedback input pin has fallen to a voltage less than the fourth threshold for a time period greater than a overload protection reset time; and

resetting the counter and the registered output to stop the blanking time function.

31. The method of claim 28 and further comprising:

after detecting that the voltage at the feedback voltage pin is greater than the fourth threshold voltage, detecting that the voltage returns to a voltage less than the fourth threshold voltage before the first blanking time elapses; and

stopping the first blanking time.

32. A circuit, comprising:

an inductor-inductor capacitor half-bridge circuit coupled a node to deliver energy to a rectifier circuit with an output;

an upper driver transistor coupling a positive power supply to the node responsive to a periodic upper gating signal;

a lower driver transistor coupling the node to a ground reference responsive to a periodic lower gating signal, the lower gating signal being complementary to and non overlapping with the upper gating signal;

a integrated circuit comprising;

an upper output pin for outputting the upper output signal having a frequency corresponding to the frequency of an on board voltage controlled oscillator (VCO);

a lower output pin for outputting the lower output signal having a frequency corresponding to the frequency of the VCO;

a feedback voltage input pin for receiving an input voltage corresponding to the output voltage of the rectifier; and

a current sense input pin for receiving a voltage corresponding to the current in the LLC half-bridge; and

wherein the integrated circuit provides a first over-current protection function by stopping the outputs of the upper and lower gating signals when the voltage at the current sense input pins exceeds a first threshold voltage and provides a second over-current protection function by modifying the frequency of the VCO when the voltage at the current sense input is greater than a second threshold voltage that is less than the first threshold voltage and modifying the frequency of the VCO when the voltage t the current sense input is less than a third threshold voltage that is less than the second threshold voltage.