Nonvolatile memory with variable read threshold

• US 7,558,109 B2
• Filed: 11/03/2006
• Issued: 07/07/2009
• Est. Priority Date: 11/03/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Brandman, Yigal
• Primary Examiner(s): Ho; Hoai V
• Application Number:
  US11/556,626
• Publication Number:
  US 20080123420A1
• Time in Patent Office: 977 Days
• Field of Search: 365/185.03, 365/185.28, 365/185.29, 365/236, 365/185.02, 365/185.22
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Data is read from a nonvolatile memory array using one or more read voltages that are adjusted during memory life. Programming target voltages and read voltages may be adjusted together over memory life to map memory states to an increasingly wide threshold window. Individual memory states are mapped to sub-ranges that are made wider, reducing errors.

Claims

1. A flash memory system comprising:

a flash memory array that includes a plurality of memory cells programmed to a plurality of programmed states;

a reading circuit connected to the memory array, the reading circuit comparing a memory cell threshold voltage to a first plurality of predetermined voltages to distinguish the plurality of programmed states in a first mode and comparing the memory cell threshold voltage to a second plurality of predetermined voltages to distinguish the plurality of programmed states in a second mode, the highest one of the second plurality of predetermined voltages being higher than the highest one of the first plurality of predetermined voltages; and

a programming circuit that programs cells to a first plurality of target voltages individually corresponding to programmed states in the first mode and programming cells to a second plurality of target voltages individually corresponding to programmed states in the second mode.

2. The flash memory system of claim 1 further comprising maintaining a record that indicates whether a portion of the memory array was programmed in the first mode or in the second mode.

3. The flash memory system of claim 1 wherein the highest one of the second plurality of target voltages is higher than the highest one of the first plurality of target voltages.

4. The flash memory system of claim 1 wherein the second plurality of target voltages are more widely spaced than the first plurality of target voltages.

5. The flash memory system of claim 1 wherein the reading circuit further distinguishes within individual ones of the plurality of programmed states to provide probability information regarding cell states.

6. The flash memory system of claim 1 further comprising a soft-input soft-output decoder.

7. The flash memory system of claim 6 wherein the flash memory system changes from the first mode to the second mode in response to a signal generated by the soft-input soft-output decoder.

8. The flash memory system of claim 1 further comprising an erase count indicator, and wherein the flash memory system changes from the first mode to the second mode when an erase count maintained by the erase count indicator exceeds a predetermined value.

9. The flash memory system of claim 1 wherein the flash memory system is in a removable memory card having a host interface.

10. The flash memory system of claim 1 wherein the first plurality of predetermined voltages define a first threshold voltage window, the second plurality of predetermined voltages define a second threshold voltage window, the second threshold voltage window being wider than the first threshold voltage window.

11. The flash memory system of claim 1 wherein each of the second plurality of predetermined voltages is more widely spaced from adjacent ones of the second plurality of voltages than a corresponding one of the first plurality of voltages is separated from adjacent ones of the first plurality of voltages.

12. The flash memory system of claim 1 wherein the second plurality of predetermined voltages are selected to balance error corrections between adjacent states.

13. The flash memory system of claim 1 wherein the reading circuit compares the memory cell threshold voltage to the first plurality of predetermined voltages in the first mode in response to a first host request for data, the reading circuit compares the memory cell threshold voltage to the second plurality of predetermined voltages in the second mode in response to a second host request for data.