NAND flash memory device

• US 7,558,118 B2
• Filed: 10/24/2007
• Issued: 07/07/2009
• Est. Priority Date: 10/24/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Futatsuyama, Takuya
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US11/923,211
• Publication Number:
  US 20080247231A1
• Time in Patent Office: 622 Days
• Field of Search: 365/185.18, 365/185.03, 365/185.17, 365/185.12
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

A NAND flash memory device includes: a memory cell array that includes a plurality of NAND memory cell units each including a connection element having a plurality of electrically-rewritable memory cells; a plurality of word lines that are connected to the plurality of memory cells; a plurality of bit lines that are connected to the plurality of memory cells; and a read-write control section that applies a voltage selectively to the plurality of word lines and the plurality of bit lines, wherein each of the plurality of NAND memory cell units includes a first select gate transistor and a second select gate transistor; and wherein the read-write control section sets an voltage level applied to word lines, so that the voltage level becomes lower than a predetermined voltage level applied to other word lines connected to control gate electrodes of memory cells.

Claims

1. A NAND flash memory device comprising:

a memory cell array that includes a plurality of NAND memory cell units each including a connection element having a plurality of electrically-rewritable memory cells;

a plurality of word lines that are connected to the plurality of memory cells;

a plurality of bit lines that are connected to the plurality of memory cells; and

a read-write control section that applies a voltage selectively to the plurality of word lines and the plurality of bit lines to perform writing, reading, or erasure of data into or from the plurality of memory cells,

wherein each of the plurality of NAND memory cell units includes a first select gate transistor connected between one end of the connection element and the bit lines and a second select gate transistor connected between the other end of the connection element and a source line; and

wherein the read-write control section sets a voltage level applied to word lines connected to the control gate electrodes of memory cells adjacent to the second select gate transistor, so that the voltage level becomes lower than a predetermined voltage level applied to other word lines connected to control gate electrodes of memory cells except the memory cells adjacent to the second select gate transistor.

2. The NAND flash memory device according to claim 1,

wherein, during erasure operation for erasing data from the memory cells adjacent to the second select gate transistor, the voltage level is an erasure verify level.

3. The NAND flash memory device according to claim 2,

wherein, during erasure operation for erasing data from the memory cells adjacent to the first select gate transistor, the voltage level is an erasure verify level.

4. The NAND flash memory device according to claim 1,

wherein, during write operation for writing data pertaining to a lower page of an even-numbered page to the memory cells adjacent to the second select gate transistor, the voltage level is a write verify level, and

wherein, when data pertaining to a lower page of an odd-numbered page of the memory cells adjacent to the second select gate transistor are not written during read operation for reading data pertaining to the lower page of the even-numbered page from the memory cells adjacent to the second select gate transistor, the voltage level is a read level.

5. The NAND flash memory device according to claim 4,

wherein, during write operation for writing data pertaining to the lower page of the even-numbered page to the memory cells adjacent to the first select gate transistor, the voltage level is the write verify level, and

wherein, when data pertaining to the lower page of the odd-numbered page of the memory cells adjacent to the first select gate transistor are not written during read operation for reading data pertaining to the lower page of the even-numbered page from the memory cells adjacent to the first select gate transistor, the voltage level is the read level.

9. The NAND flash memory device according to claim 1,

wherein, during write operation for writing data pertaining to an upper page of an even-numbered page into the memory cells adjacent to the second select gate transistor, the voltage level is a write verify level, and

wherein, when data pertaining to an upper page of an odd-numbered page of the memory cells adjacent to the second select gate transistor are not written during read operation for reading data pertaining to the upper page of the even-numbered page from the memory cells adjacent to the second select gate transistor, the voltage level is a read level.

10. The NAND flash memory device according to claim 9,

wherein, during write operation for writing data pertaining to the upper page of the even-numbered page into the memory cells adjacent to the first select gate transistor, the voltage level is the write verify level, and

wherein, when data pertaining to the upper page of the odd-numbered page of the memory cells adjacent to the first select gate transistor are not written during read operation for reading data pertaining to the upper page of the even-numbered page from the memory cells adjacent to the first select gate transistor, the voltage level is the read level.

11. The NAND flash memory device according to claim 1,

wherein, during write operation for writing data pertaining to a lower page of an odd-numbered page into the memory cells adjacent to the second select gate transistor, the voltage level is a write verify level, and

wherein, when data pertaining to an upper page of an odd-numbered page of the memory cells adjacent to the second select gate transistor are not written during read operation for reading data pertaining to the upper page of the odd-numbered page from the memory cells adjacent to the second select gate transistor, the voltage level is a read level.

12. The NAND flash memory device according to claim 11,

wherein, during write operation for writing data pertaining to the lower page of the odd-numbered page into the memory cells adjacent to the first select gate transistor, the voltage level is the write verify level, and

wherein, when data pertaining to the upper page of the odd-numbered page of the memory cells adjacent to the first select gate transistor are not written during read operation for reading data pertaining to the upper page of the odd-numbered page from the memory cells adjacent to the first select gate transistor, the voltage level is the read level.

15. The NAND flash memory device according to claim 1,

wherein, when data pertaining to an upper page of an even-numbered page of the memory cells adjacent to the second select gate transistor are written during read operation for reading data pertaining to an upper page of an odd-numbered page from the memory cells adjacent to the second select gate transistor, the voltage level is a read level.

16. The NAND flash memory device according to claim 15,

wherein, when data pertaining to the upper page of the even-numbered page of the memory cells adjacent to the first select gate transistor are written during read operation for reading data pertaining to the upper page of the odd-numbered page from the memory cells adjacent to the first select gate transistor, the voltage level is the read level.

17. The NAND flash memory device according to claim 1,

wherein, when the voltage level is set lower than the predetermined voltage level, the voltage level is 0.

6. A NAND flash memory device comprising:

a memory cell array that includes a plurality of NAND memory cell units each including a connection element having a plurality of electrically-rewritable memory cells;

a plurality of word lines that are connected to the plurality of memory cells;

a plurality of bit lines that are connected to the plurality of memory cells; and

a read-write control section that applies a voltage selectively to the plurality of word lines and the plurality of bit lines to perform writing, reading, or erasure of data into or from the plurality of memory cells,

wherein each of the plurality of NAND memory cell units includes a first select gate transistor connected between one end of the connection element and the bit lines and a second select gate transistor connected between the other end of the connection element and a source line; and

wherein the read-write control section sets a voltage level applied to the word lines connected to the control gate electrodes of memory cells adjacent to the second select gate transistor, so that the voltage level becomes higher than a predetermined voltage level applied to other word lines connected to control gate electrodes of memory cells except the memory cells adjacent to the second select gate transistor.

7. The NAND flash memory device according to claim 6,

wherein, when data pertaining to a lower page of an odd-numbered page of the memory cells adjacent to the second select gate transistor are written during read operation for reading data pertaining to a lower page of an even-numbered page from the memory cells adjacent to the second select gate transistor, the voltage level is a read level.

8. The NAND flash memory device according to claim 7,

wherein, when data pertaining to the lower page of the odd-numbered page of the memory cells adjacent to the first select gate transistor are written during read operation for reading data pertaining to the lower page of the even-numbered page from the memory cells adjacent to the first select gate transistor, the voltage level is the read level.

13. The NAND flash memory device according to claim 6,

wherein, when data pertaining to an upper page of an odd-numbered page of the memory cells adjacent to the second select gate transistor are written during read operation for reading data pertaining to an upper page of an even-numbered page from the memory cells adjacent to the second select gate transistor, the voltage level is a read level.

14. The NAND flash memory device according to claim 6,

wherein, when data pertaining to the upper page of the odd-numbered page of the memory cells adjacent to the first select gate transistor are written during read operation for reading data pertaining to the upper page of the even-numbered page from the memory cells adjacent to the first select gate transistor, the voltage level is the read level.