System and method for clock replication using reference clock

• US 7,558,275 B2
• Filed: 09/13/2005
• Issued: 07/07/2009
• Est. Priority Date: 09/13/2005
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.), Sony Pictures Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Champion, Mark
• Primary Examiner(s): Moe; Aung S
• Assistant Examiner(s): RIYAMI, ABDULLA A
• Application Number:
  US11/226,087
• Publication Number:
  US 20070058078A1
• Time in Patent Office: 1,393 Days
• Field of Search: 370/468, 370/477, 370/503, 370/229, 370/230, 370/230.1, 370/231, 370/310, 370/395.62, 348/473, 348/512, 348/518, 348/138, 348/500, 348/537, 348/E7.021, 348/E7.02, 340/5.63, 386/E9.062
• US Class Current: 370/395.62
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 5/06 Generation of synchronising signals

Abstract

Data encoded with a video clock is transmitted over a communication link in accordance with a communication reference signal, which in one embodiment is a wireless link. In one embodiment, the video clock is independent from the communication reference signal. The communication reference clock, which may be known to both the transmitter and receiver, is used to determine a frame period. On the receiver-side, the number of video cycles of the video data which are actually received are counted. The video clock may then be regenerated using the determined frame period and counted video clock cycles.

Claims

1. A method of regenerating a data clock signal comprising:

receiving data encoded with said data clock signal over a communication link according to a communication reference clock;

counting a number of data clock cycles received over said communication link;

determining a frame period for said data using said communication reference clock;

regenerating said data clock signal using said number of data clock cycles and said frame period; and

reducing jitter in said data by time averaging said number of data clock cycles, wherein said time averaging includes;

(a) adding values for said number of data clock cycles to provide an accumulated value,

(b) dividing said accumulated value by an integer to provide an averaged value,

(c) using said averaged value to perform said regenerating,

(d) subtracting said averaged value from said accumulated value to provide an updated accumulated value, and

(e) repeating (a)-(e) on a continuous basis.

2. The method of claim 1, wherein said communication link is a wireless communication link.

3. The method of claim 1, wherein said data is high definition video data, and said data clock signal is associated with an encoding process of said high definition video data.

4. The method of claim 1, wherein said data clock signal is not based on said communication reference clock.

5. The method of claim 1, wherein said regeneration further comprises using a phase detector to i) receive a first value representative of said communication reference signal, ii) receive a second value representative of said number of data clock cycles, and iii) provide an input to a voltage controlled oscillator, said voltage controlled oscillator outputting a signal representative of said data clock signal.

6. The method of claim 1, wherein determining the frame period comprises dividing said communication reference clock by a predetermined integer that is between 200 and 2000.

7. The method of claim 1, further comprising:

updating, continuously, said number of data clock cycles; and

updating, continuously, said data clock signal based on said continuously updated number of data clock cycles.

8. A method of regenerating a video clock signal comprising:

receiving video data encoded with said video clock signal over a communication link, said communication link having a communication reference clock associated therewith that is independent of said video clock signal, and said video data being encoded with said video clock signal prior to being transmitted over said communication link;

counting, by a receiver-side device, a number of video clock cycles of said video data received over said communication link;

determining a frame period for said video data using said communication reference clock;

regenerating, by said receiver side device, said video clock signal using said number of video clock cycles and said frame period; and

reducing jitter in said video data by time averaging said number of video clock cycles, wherein said time averaging includes;

(a) adding values for said number of video clock cycles to provide an accumulated value,

(b) dividing said accumulated value by an integer to provide an averaged value,

(c) using said averaged value to perform said regenerating,

(d) subtracting said averaged value from said accumulated value to provide an undated accumulated value, and

(e) repeating (a)-(e) on a continuous basis.

9. The method of claim 8, wherein said communication link is a wireless communication link.

10. The method of claim 8, wherein said video data is high definition video data, and said video clock signal is associated with an encoding process of said high definition video data.

11. The method of claim 8, wherein said regeneration further comprises:

receiving, by a phase detector, a first value representative of said communication reference signal; and

receiving, by a phase detector, a second value representative of said number of video clock cycles; and

providing input to a voltage controlled oscillator, wherein said voltage controlled oscillator is to output a signal representative of said video clock signal.

12. The method of claim 8, wherein determining the frame period comprises dividing said communication reference clock by a predetermined integer that is between 200 and 2000.

13. The method of claim 8, further comprising:

updating, continuously, said number of video clock cycles; and

updating, continuously, said video clock signal based on said continuously updated number of video clock cycles.

14. A system for regenerating a data clock signal comprising:

a transmitter to transmit data encoded with said data clock signal; and

a receiver to receive said data over a communication link, said communication link having a communication reference clock that is not based on said data clock signal, said receiver to,

count a number of data clock cycles received from said transmitter over said communication link;

determine a frame period for said data using said communication reference clock;

regenerate said data clock signal using said number of data clock cycles and said frame period; and

reduce jitter in said data by time averaging said number of data clock cycles, wherein the receiver is configured to perform said time averaging by;

(a) adding values for said number of data clock cycles to provide an accumulated value,

(b) dividing said accumulated value by an integer to provide an averaged value,

(c) using said averaged value to perform said regenerating,

(d) subtracting said averaged value from said accumulated value to provide an undated accumulated value,

(e) repeating (a)-(e) on a continuous basis.

15. The system of claim 14, wherein said communication link is a wireless communication link.

16. The system of claim 14, wherein said data is high definition video data, and said data clock signal is associated with an encoding process of said high definition video data.

17. The system of claim 14, wherein said receiver is coupled to a display device, and said regenerated data clock signal is provided to said display device to decode said data.

18. The system of claim 14, wherein said receiver further includes a phase detector to:

receive a value representative of said communication reference signal;

receive a value representative of said number of data clock cycles; and

output a phase shift signal to a voltage controlled oscillator, wherein said voltage controlled oscillator, in response to said phase shift signal, is to output a signal representative of said data clock signal.

19. The system of claim 14, wherein said receiver is to determine said frame period by dividing said communication reference clock by a predetermined integer that is between 200 and 2000, wherein said integer is known to both said transmitter and said receiver.

20. The system of claim 14, wherein said receiver is further to continuously update said number of data clock cycles, and continuously update said data clock signal based on said continuously updated number of data clock cycles.