System and method for detecting integrated circuit pattern defects

• US 7,558,419 B1
• Filed: 08/12/2004
• Issued: 07/07/2009
• Est. Priority Date: 08/14/2003
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV), Board of Trustees of the Leland Stanford Junior University (Stanford University)
• Original Assignee: Brion Technologies Incorporated (ASML Holding NV)
• Inventors: Pease, R. Fabian, Ye, Jun, Cao, Yu
• Primary Examiner(s): Bella; Matthew C.
• Assistant Examiner(s): PERUNGAVOOR, SATHYANARAYA V
• Application Number:
  US10/917,060
• Time in Patent Office: 1,790 Days
• Field of Search: 382141-152, 382/209
• US Class Current: 382/144
• CPC Class Codes: G03F 1/84 Inspecting
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/001 using an image reference approach

Abstract

There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for inspecting integrated circuits, including, for example, patterns projected, provided or formed on a wafer using photomasks, or patterns on the photomask itself. The inspection system and technique of this aspect includes first identifying, determining and/or detecting areas and/or patterns that are potentially defective by removing, filtering and/or eliminating from a set of potential defects any and/or all typical, regular or normal patterns. The identification, determination and/or detection of potential defects may be performed relatively quickly by a rapidly executing algorithm. In this way, a first or “coarse” analysis is performed rapidly and some, many, all or substantially all of the regular, normal or typical patterns are eliminated from further analysis. Thereafter, a second more detailed analysis is performed. This second analysis focuses on the set of potential defects that were identified, determined and/or detected during the first analysis of the photomask or wafer (i.e., the “coarse” analysis). The second analysis may be considerably a more detailed or a “fine” analysis relative to the first or “coarse” analysis. Indeed, in one embodiment, the second analysis may implement a more computational intensive process, without sacrificing throughput, since only a small portion of the photomask or wafer is inspected in the second analysis. In this way, the detailed analysis of the defect candidates may identify (i) all or substantially all of the actual defects and/or (ii) only the actual defects from the potential defects identified during the first analysis.

Claims

1. A method for inspecting a photomask used to generate integrated circuit patterns on a wafer, the method comprising:

a computer performing steps comprising;

generating a potentially defective circuit pattern set, having a plurality of potentially defective circuit patterns including a first circuit pattern that is defective and a second circuit pattern that is valid, wherein generating the potentially defective circuit pattern set includes;

applying an algorithm to data representative of images of a plurality of circuit patterns to generate data representative of images of valid circuit patterns and

comparing the data representative of images of a plurality of circuit patterns to the data representative of images of valid circuit patterns to identify at least one potentially defective circuit pattern; and

determining a defective circuit pattern in the potentially defective circuit pattern set using a codebook including codes representative of known valid circuit patterns or codes representative of known invalid circuit patterns.

2. The method of claim 1 further including generating an image of at least a portion of the photomask including an image of the plurality of circuit patterns.

3. The method of claim 2 wherein generating an image of at least a portion of the photomask includes measuring intensity data, in situ, using an image sensor having a plurality of sensor cells.

4. The method of claim 2 wherein generating an image of at least a portion of the photomask includes simulating the image using information in a mask database.

5. The method of claim 4 wherein simulating the image using information in a mask database includes converting a plurality of polygons, including resolution enhancement technology, to a pixel-based bitmap representation thereof.

6. The method of claim 2 wherein the data representative of the images of a plurality of circuit patterns are pixel-based bitmap representations thereof.

7. The method of claim 6 wherein the algorithm includes a lossy compression algorithm and a decompression algorithm such that the data representative of images of valid circuit patterns is data representative of decompressed lossy compressed images.

8. The method of claim 7 wherein:

comparing the data representative of images of a plurality of circuit patterns to the data representative of images of valid circuit patterns to identify the at least one potentially defective circuit pattern includes subtracting the data representative of the decompressed lossy compressed images from the data representative of images of the plurality of circuit patterns; and

the method further includes determining if the difference between the data representative of the decompressed lossy compressed images and the data representative of images of the plurality of circuit patterns exceeds a predetermined threshold.

9. The method of claim 1 wherein determining a defective circuit pattern in the potentially defective circuit pattern set includes using a knowledge base having valid circuit pattern images or information representative of valid circuit patterns.

10. The method of claim 1 wherein determining a defective circuit pattern in the potentially defective circuit pattern set further includes comparing the plurality of potentially defective circuits of the potentially defective circuit pattern set to a knowledge base having valid circuit pattern images or information representative of valid circuit patterns.

11. The method of claim 10 further including continuously, periodically or intermittently updating the knowledge base with valid circuit pattern images or information representative of valid circuit patterns.

12. The method of claim 1 wherein determining a defective circuit pattern in the potentially defective circuit pattern set further includes comparing the plurality of potentially defective circuit patterns of the potentially defective circuit pattern set to a knowledge base having invalid circuit pattern images or information representative of invalid circuit patterns.

13. The method of claim 12 wherein the knowledge base is continuously, periodically or intermittently updated with invalid circuit pattern images or information representative of invalid circuit patterns.

14. The method of claim 1 further including selecting the codebook from a plurality of codebooks.

15. The method of claim 14 wherein selecting the codebook from a plurality of codebooks includes selecting the codebook on the basis of a type of circuit defect.

16. The method of claim 14 wherein the codebook includes an edge-shape code-space.

17. The method of claim 14 wherein the codebook includes an N×

M image patch or region code-space.

18. An inspection system to inspect a photomask used to generate integrated circuit patterns on a wafer, the system comprising:

a user interface unit;

a data storage unit;

a data processing unit, coupled to the user interface unit and the data storage unit, to identify a defective circuit pattern in an integrated circuit pattern, the data processing unit configured to;

generate a potentially defective circuit pattern set, having a plurality of potentially defective circuit patterns including a first circuit pattern that is defective and a second circuit pattern that is valid, by applying an algorithm to data representative of images of a plurality of circuit patterns to generate data representative of images of valid circuit patterns and comparing the data representative of images of a plurality of circuit patterns to the data representative of images of valid circuit patterns to identify at least one potentially defective circuit pattern; and

determine a defective circuit pattern in the potentially defective circuit pattern set using a codebook including codes representative of known valid circuit patterns or codes representative of known invalid circuit patterns.

19. The system of claim 18 wherein the algorithm includes a lossy compression algorithm and a decompression algorithm such that the data representative of images of valid circuit patterns is data representative of decompressed lossy compressed images.

20. The system of claim 19 wherein the data processing unit is configured to compares data representative of images of a plurality of circuit patterns to data representative of images of a plurality of valid patterns to identify the at least one circuit pattern that is potentially defective by subtracting the data representative of the decompressed lossy compressed images from the data representative of images of the plurality of circuit patterns.

21. The system of claim 20 wherein the data processing unit is configured to determine if the difference between the data representative of the decompressed lossy compressed images and the data representative of images of the plurality of circuit patterns exceeds a predetermined threshold.

22. The system of claim 18 wherein the data processing unit is configured to determine a defective circuit pattern in the potentially defective circuit pattern set using a knowledge base having valid circuit pattern images or information representative of valid circuit patterns.

23. The system of claim 18 wherein the data processing unit is configured to determine a defective circuit pattern in the potentially defective circuit pattern set by comparing the plurality of potentially defective circuit patterns of the potentially defective circuit pattern set to a knowledge base having valid circuit pattern images or information representative of valid circuit patterns.

24. The system of claim 23 wherein the data processing unit is configured to continuously, periodically or intermittently updates the knowledge base with valid circuit pattern images or information representative of valid circuit patterns.

25. The system of claim 18 wherein the data processing unit is configured to determine a defective circuit pattern in the potentially defective circuit pattern set by comparing the plurality of potentially defective circuit patterns of the potentially defective circuit pattern set to a knowledge base having invalid circuit pattern images or information representative of invalid circuit patterns.

26. The system of claim 25 wherein the data processing unit is configured to continuously, periodically or intermittently update the knowledge base with invalid circuit pattern images or information representative of invalid circuit patterns.

27. The system of claim 18 wherein the data processing unit is configured to select the codebook from a plurality of codebooks.

28. The system of claim 27 wherein the data processing unit is configured to select the codebook from a plurality of codebooks on the basis of a type of circuit defect.

29. The system of claim 27 wherein the codebook includes an edge-shape code-space.

30. The system of claim 27 wherein the codebook includes an N×

M image patch or region code-space.

31. The system of claim 18 wherein the data processing unit is configured to generate an image of at least a portion of the photomask, including an image of the plurality of circuit patterns.

32. The system of claim 31 further including an image sensor, having a plurality of sensor cells, to measure intensity data representative of the image of the photomask and wherein the data processing unit is configured to generate an image of at least a portion of the photomask using the intensity data.

33. The system of claim 31 wherein the data processing unit is configured to generate an image of at least a portion of the photomask by simulating the image using information in a mask database.

34. The system of claim 33 wherein simulating the image using information in a mask database includes converting a plurality of polygons, including resolution enhancement technology, to a pixel-based bitmap representation thereof.

35. The system of claim 31 wherein the data representative of the images of a plurality of circuit patterns are pixel-based bitmap representations thereof.