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System and method for detecting integrated circuit pattern defects

  • US 7,558,419 B1
  • Filed: 08/12/2004
  • Issued: 07/07/2009
  • Est. Priority Date: 08/14/2003
  • Status: Active Grant
First Claim
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1. A method for inspecting a photomask used to generate integrated circuit patterns on a wafer, the method comprising:

  • a computer performing steps comprising;

    generating a potentially defective circuit pattern set, having a plurality of potentially defective circuit patterns including a first circuit pattern that is defective and a second circuit pattern that is valid, wherein generating the potentially defective circuit pattern set includes;

    applying an algorithm to data representative of images of a plurality of circuit patterns to generate data representative of images of valid circuit patterns andcomparing the data representative of images of a plurality of circuit patterns to the data representative of images of valid circuit patterns to identify at least one potentially defective circuit pattern; and

    determining a defective circuit pattern in the potentially defective circuit pattern set using a codebook including codes representative of known valid circuit patterns or codes representative of known invalid circuit patterns.

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