Integrated circuit and method of generating a bias current for a plurality of data transceivers

• US 7,558,552 B1
• Filed: 11/19/2004
• Issued: 07/07/2009
• Est. Priority Date: 11/19/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lee, Thomas Anthony
• Primary Examiner(s): Anderson; Matthew D
• Assistant Examiner(s): Dao; Minh D
• Application Number:
  US10/993,607
• Time in Patent Office: 1,691 Days
• Field of Search: 455/259, 455/127.1, 455/169.1, 455/195.1, 375/219, 375/354, 375/355, 327141-148
• US Class Current: 455/259
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling

Abstract

Various embodiments of the present invention relate to circuits for and methods of generating a bias current for a plurality of data transceivers on an integrated circuit. According to one embodiment, an integrated circuit having a plurality of data transceivers comprises a first data transceiver receiving a reference voltage. A plurality of data transceivers are preferably coupled to the first data transceiver, where each the data transceiver of the plurality of data transceivers receives a reference current based upon the reference voltage from the first data transceiver. According to alternate embodiment of the invention, an external resistor is coupled to a data transceiver to generate a fixed bias current in addition to a variable bias current. A method of generating a bias current for a plurality of data transceivers is also disclosed.

Claims

1. An integrated circuit having a plurality of data transceivers, said integrated circuit comprising:

a reference voltage;

a first data transceiver receiving said reference voltage;

a plurality of data transceivers coupled to said first data transceiver, each data transceiver of said plurality of data transceivers receiving a reference current from said first data transceiver, said reference current being based upon said reference voltage;

a current mirror associated with each said data transceiver, said current mirror propagating said reference current; and

a plurality of switches coupled to each said current mirror, said plurality of switches enabling the configuration of each said data transceiver in either a master mode or a slave mode.

2. The integrated circuit of claim 1 wherein said plurality of switches coupled to said current mirror associated with said first data transceiver couples said reference current to said plurality of data transceivers.

3. The integrated circuit of claim 1 wherein each said data transceiver configured in a slave mode receives said reference current from an adjacent data transceiver.

4. An integrated circuit having a plurality of data transceivers, said integrated circuit comprising:

a reference voltage;

a master data transceiver receiving said reference voltage and generating a reference current based upon said reference voltage; and

a plurality of slave data transceivers coupled to said master data transceiver, each said slave transceiver receiving said reference current from said master data transceiver; and

current mirrors associated with said master data transceiver and said plurality of slave data transceivers, said current mirrors propagating said reference current.

5. The integrated circuit of claim 4 wherein said master data transceiver and said slave data transceivers are arranged in a column.

6. The integrated circuit of claim 5 wherein said master data transceiver comprises a switching circuit for outputting a reference current to an adjacent data transceiver.

7. The integrated circuit of claim 5 wherein each slave transceiver of said plurality of slave transceivers comprises a switching circuit for receiving said reference current from an adjacent data transceiver.

8. The integrated circuit of claim 4 further comprising a data bus coupling each said data transceiver to an adjacent data transceiver and enabling the coupling of said reference current between said data transceivers.

9. An integrated circuit having a plurality of data transceivers, said integrated circuit comprising:

a reference voltage coupled to a first node;

an external resistor coupled to second node;

a master data transceiver receiving said reference voltage, said master data transceiver comprising a fixed biasing block generating a fixed reference current based upon said reference voltage and said external resistor, and a variable biasing block generating a variable reference current based upon said reference voltage; and

a plurality of slave data transceivers coupled to said master data transceiver, each said slave data transceiver of said plurality of slave data transceivers receiving said fixed reference current and said variable reference current from said master data transceiver.

10. The integrated circuit of claim 9 wherein said master data transceiver and said plurality of slave data transceivers are arranged in a column.

11. The integrated circuit of claim 10 further comprising a bus coupling each said slave data transceiver to said mater data transceiver.

12. The integrated circuit of claim 9 further comprising a first plurality of circuits coupled to receive said fixed reference current.

13. The integrated circuit of claim 12 further comprising a second plurality of circuits coupled to receive said variable reference current.

14. An integrated circuit having a plurality of data transceivers, said integrated circuit comprising:

a first plurality of data transceivers positioned in a column on a first end of said integrated circuit and having a master data transceiver and a plurality of slave data transceivers;

a reference voltage coupled to said master data transceiver;

a reference current generated by said master data transceiver; and

a bus coupling said master data transceiver to said plurality of slave data transceivers,

wherein said reference current comprises a variable reference current which varies based upon the resistance of a polysilicon layer of said integrated circuit.

15. The integrated circuit of claim 14 further comprising an external resistor coupled to said master data transceiver.

16. The integrated circuit of claim 15 wherein said master data transceiver generates a fixed reference current based upon said reference voltage and said external resistor.

17. The integrated circuit of claim 14 further comprising a second plurality of data transceivers positioned in a column on a second end of an integrated circuit.

18. A method of generating a bias current for a plurality of data transceivers, said method comprising the steps of:

positioning said plurality of data transceivers in a column;

coupling a reference voltage to a first data transceiver of said plurality of data transceivers;

generating a first bias current based upon said reference voltage; and

coupling, using a switch that configures said first data transceiver in either a master mode or a slave mode, said first bias current from said first data transceiver to the other data transceiver of said plurality of data transceivers.

19. The method of claim 18 further comprising a step of coupling an external resistor to said first data transceiver.

20. The method of claim 19 further comprising a step of generating a second bias current based upon said reference voltage and said external resistor.

21. The method of claim 18 wherein said step of positioning said plurality of data transceivers in a column comprises a step of positioning said plurality of data transceivers in a column on an end of said integrated circuit.

22. The method of claim 21 further comprising a step of providing a bus between said plurality of data transceivers.

23. A method of generating a bias current for a plurality of data transceivers, said method comprising the steps of:

providing a master data transceiver;

coupling a plurality of slave data transceivers to said master data transceiver by way of a bus; and

coupling, using switches that configure said data transceivers in either a master mode or a slave mode, a first reference current generated in said master data transceiver to said plurality of slave data transceivers.

24. The method of claim 23 further comprising a step of coupling a resistor to said master data transceiver, wherein said first reference current comprises a fixed reference current based upon said reference voltage and said resistor.

25. The method of claim 24 further comprising a step of generating a second reference current based upon said reference voltage and an internal resistor.

26. The method of claim 23 further comprising a step of arranging said master data transceiver and said plurality of slave data transceivers in a column.

27. The method of claim 26 wherein said step of coupling a first reference current comprises providing a bus between said master data transceiver and said plurality of slave data transceivers.

28. A method of generating a bias current for a plurality of data transceivers, said method comprising the steps of:

providing a plurality of data transceivers in a column;

coupling a reference voltage to a predetermined data transceiver of said plurality of data transceivers;

generating a first reference current based upon said reference voltage; and

coupling, using switches that configure said plurality of data transceivers in either a master mode or a slave mode, said first reference current from said predetermined data transceiver to each other data transceiver.

29. The method of claim 28 wherein said step of providing a plurality of data transceivers in a column comprises a step of providing a plurality of data transceivers in a column on an end of a programmable logic device.

30. The method of claim 28 further comprising a step of coupling an external resistor to said predetermined data transceiver.

31. The method of claim 30 further comprising a step of generating a second reference current based upon said reference voltage and said external resistor.

32. The method of claim 31 further comprising a step of coupling said second reference current from said predetermined data transceiver to each other data transceiver.