Generating a hardware description of a block diagram model for implementation on programmable hardware

• US 7,558,711 B2
• Filed: 12/05/2006
• Issued: 07/07/2009
• Est. Priority Date: 08/18/1997
• Status: Expired due to Fees

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Kodosky, Jeffrey L., Butler, Cary P., Odom, Brian K., Andrade, Hugo
• Primary Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US11/566,782
• Publication Number:
  US 20070198236A1
• Time in Patent Office: 945 Days
• Field of Search: 703/2, 703/22, 717/106, 717/125, 717/140, 702/57, 702/119, 702/119.57, 702/123, 702/127, 716/1, 716 16- 18, 345/700, 345/711
• US Class Current: 703/2
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 8/34 Graphical or visual programming

Abstract

A computer-implemented system and method for generating a hardware implementation of graphical code. The method comprises first creating a graphical program. A first portion of the graphical program may optionally be compiled into machine code for execution by a CPU. A second portion of the graphical program is converted into a hardware implementation according to the present invention. The operation of converting the graphical program into a hardware implementation comprises exporting the second portion of the graphical program into a hardware description, wherein the hardware description describes a hardware implementation of the second portion of the graphical program, and then configuring a programmable hardware element utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the second portion of the graphical program.

Claims

1. A computer-implemented method, the method comprising:

in a computer, creating a block diagram, wherein the block diagram implements a model of a system, wherein the block diagram comprises a plurality of interconnected nodes that visually represent functionality of the model;

generating a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram;

configuring a programmable hardware element utilizing the hardware description to produce a configured programmable hardware element, wherein the configured programmable hardware element implements a hardware implementation of the model; and

displaying one or more panels on a display for displaying output from the model in response to execution of the configured programmable hardware element.

2. The computer-implemented method of claim 1,

wherein the one or more panels comprise a graphical user interface.

3. The computer-implemented method of claim 1, further comprising:

displaying one or more second panels on the display for providing input to the model during execution of the configured programmable hardware element.

4. The computer-implemented method of claim 3, further comprising:

receiving user input to at least one of the one or more second panels during execution of the configured programmable hardware element;

providing the user input to the configured programmable hardware element; and

the configured programmable hardware element adjusting operation of the model in response to the user input.

5. The computer-implemented method of claim 1, wherein the one or more panels are created with the block diagram.

6. The computer-implemented method of claim 1, wherein the block diagram is a data flow diagram.

7. The computer-implemented method of claim 1, wherein the block diagram implements a model of a physical system.

8. The computer implemented method of claim 1,

wherein the block diagram has associated data structures which represent the block diagram;

and

wherein said generating the hardware description comprises;

traversing the data structures; and

converting the data structures into a hardware description format in response to said traversing.

9. The computer implemented method of claim 1, wherein the block diagram includes a plurality of interconnected icons, and wherein the plurality of interconnected icons includes one or more function nodes and one or more icons representing at least one constant.

10. The computer implemented method of claim 1, wherein the block diagram includes a plurality of interconnected icons, and wherein the plurality of interconnected icons includes one or more function nodes and one or more icons representing at least one global variable.

11. The computer implemented method of claim 1, wherein the block diagram includes a plurality of interconnected icons, and wherein the plurality of interconnected icons includes one or more function nodes and one or more icons representing at least one input to the block diagram.

12. The computer implemented method of claim 1, wherein the block diagram includes a plurality of interconnected icons, and wherein the plurality of interconnected icons includes one or more function nodes and one or more icons representing at least one output from the block diagram.

13. The computer implemented method of claim 1, wherein the block diagram includes a plurality of interconnected icons, wherein the plurality of interconnected icons includes one or more function nodes and one or more icons representing at least one sub-program node.

14. The computer implemented method of claim 1, wherein said generating the hardware description comprises converting each of said plurality of interconnected nodes into a hardware description format.

15. The computer implemented method of claim 1,

wherein the block diagram includes a plurality of nodes, wherein at least a subset of the plurality of nodes are connected to indicate data flow among the at least a subset of the plurality of nodes, wherein the plurality of nodes includes at least one node that represents control flow of data among one or more of the plurality of nodes.

16. The computer implemented method of claim 15,

wherein the at least one node indicates one or more of iteration, looping, and/or conditional branching for the one or more of the plurality of nodes in the block diagram.

17. The computer implemented method of claim 15,

wherein the at least one node indicates iteration for the one or more of the plurality of nodes in the block diagram.

18. The computer implemented method of claim 15,

wherein the at least one node indicates looping for the one or more of the plurality of nodes in the block diagram.

19. The computer implemented method of claim 15,

wherein the at least one node indicates conditional branching for the one or more of the plurality of nodes in the block diagram.

20. The computer implemented method of claim 15,

wherein the at least one node indicates a first portion of the block diagram, wherein the at least one node indicates one of iteration, looping or conditional branching for the first portion of the block diagram.

21. The computer implemented method of claim 15,

wherein the at least one node is a structure node.

22. The computer implemented method of claim 15,

wherein the at least one node includes an interior portion, wherein a first portion of the block diagram is comprised in the interior portion, and wherein the first portion of the block diagram comprised in the interior portion of the at least one node executes according to control flow as indicated by the at least one node.

23. The computer implemented method of claim 15, wherein said generating includes examining one or more node parameters associated with the at least one node, and wherein said generating uses the one or more node parameters in generating the hardware description.

24. The computer implemented method of claim 23, wherein the at least one node is one of an iteration node or a looping node;

wherein the at least one node includes at least one of a period parameter and a phase delay parameter, wherein the period parameter indicates a period of execution for cycles of the at least one node, and wherein the phase delay parameter indicates a phase delay of cycles of the at least one node.

25. The computer implemented method of claim 15, wherein the at least one node is an iteration node, wherein the iteration node indicates iteration of the one or more of the plurality of nodes in the block diagram for a plurality of times;

wherein the iteration node includes an iteration number which indicates a number of iterations for the block diagram; and

wherein said generating uses the iteration number in generating the hardware description.

26. The computer implemented method of claim 15, wherein the at least one node is a looping node, wherein the looping node indicates looping of the one or more of the plurality of nodes in the block diagram for a plurality of times;

wherein the looping node includes a loop condition which indicates a number of executions for the block diagram; and

wherein said generating uses the loop condition in generating the hardware description.

27. The computer implemented method of claim 15, wherein said generating the hardware description based on the block diagram comprises converting each of said nodes into a hardware description format;

wherein, for said at least one node, said converting comprises;

determining inputs and outputs to/from the at least one node;

creating a hardware description of a control block which performs the control function indicated by the at least one node;

traversing input dependencies of the node; and

creating a hardware description of an AND gate, including listing connections of said input dependencies of the node to said AND gate.

28. The computer implemented method of claim 1,

wherein said generating the hardware description includes using information that is specific to a type of programmable hardware element.

29. The computer implemented method of claim 1,

wherein said generating the hardware description comprises using pre-compiled function blocks for one or more of the nodes.

30. A computer readable memory medium comprising program instructions, wherein the program instructions are executable to:

create a block diagram on a display, wherein the block diagram implements a model of a system, wherein the block diagram comprises a plurality of interconnected nodes;

generate a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram;

configure a programmable hardware element utilizing the hardware description to produce a configured programmable hardware element, wherein the configured programmable hardware element implements a hardware implementation of the model; and

display one or more panels on a display for displaying output from the model in response to execution of the configured programmable hardware element.

31. A system which generates a hardware implementation of a block diagram, the system comprising:

a computer system comprising a processor and memory, wherein the memory stores a block diagram, wherein the block diagram implements a model of a system;

wherein the memory also stores a software program which is executable to generate a hardware description based on at least a portion of the block diagram, and wherein the hardware description describes a hardware implementation of the at least a portion of the block diagram;

a device coupled to the computer system, wherein the device includes a programmable hardware element;

wherein the computer system is operable to configure the programmable hardware element utilizing the hardware description to produce a configured hardware element, and wherein the configured hardware element implements a hardware implementation of the at least a portion of the block diagram; and

a display coupled to at least one of the computer system and the device, wherein the display is operable to display one or more panels for displaying output from the model in response to execution of the configured programmable hardware element.

32. A computer-implemented method, the method comprising:

in a computer, creating a block diagram, wherein the block diagram implements a model of a system, wherein the block diagram comprises a plurality of interconnected nodes, wherein at least a subset of the plurality of nodes are connected to indicate data flow among the at least a subset of the plurality of nodes, wherein the plurality of nodes includes at least one node that represents control flow of data among one or more of the plurality of nodes;

generating a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram;

configuring a programmable hardware element utilizing the hardware description to produce a configured programmable hardware element, wherein the configured programmable hardware element implements a hardware implementation of the model.

33. The method of claim 32, further comprising:

displaying one or more panels on a display for displaying output from the model in response to execution of the configured programmable hardware element.

34. The method of claim 32,

wherein said generating the hardware description comprises using pre-compiled function blocks for one or more of the nodes.

35. A computer readable memory medium comprising program instructions, wherein the program instructions are executable to:

create a block diagram, wherein the block diagram implements a model of a system, wherein the block diagram comprises a plurality of interconnected nodes, wherein at least a subset of the plurality of nodes are connected to indicate data flow among the at least a subset of the plurality of nodes, wherein the plurality of nodes includes at least one node that represents control flow of data among one or more of the plurality of nodes;

generate a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram;

wherein the hardware description is useable to configure a programmable hardware element to produce a configured programmable hardware element, wherein the configured programmable hardware element implements a hardware implementation of the model.

36. The computer readable memory medium of claim 35, wherein the program instructions are further executable to:

display one or more panels on a display for displaying output from the model in response to execution of the configured programmable hardware element.

37. The computer readable memory medium of claim 35,

wherein in generating the hardware description, the program instructions are executable to use pre-compiled function blocks for one or more of the nodes.

38. A system which generates a hardware implementation of a block diagram, the system comprising:

a computer system comprising a processor and memory, wherein the memory stores a block diagram, wherein the block diagram implements a model of a system, wherein the block diagram comprises a plurality of interconnected nodes, wherein at least a subset of the plurality of nodes are connected to indicate data flow among the at least a subset of the plurality of nodes, wherein the plurality of nodes includes at least one node that represents control flow of data among one or more of the plurality of nodes

wherein the memory also stores a software program which is executable to generate a hardware description based on at least a portion of the block diagram, and wherein the hardware description describes a hardware implementation of the at least a portion of the block diagram;

a device coupled to the computer system, wherein the device includes a programmable hardware element;

wherein the computer system is operable to configure the programmable hardware element utilizing the hardware description to produce a configured hardware element, and wherein the configured hardware element implements a hardware implementation of the at least a portion of the block diagram.

39. The system of claim 38, further comprising:

a display coupled to at least one of the computer system and the device, wherein the display is operable to display one or more panels for displaying output from the model in response to execution of the configured programmable hardware element.

40. The system of claim 38,

wherein in generating the hardware description, the software program is executable to use pre-compiled function blocks for one or more of the nodes.

41. A computer readable memory medium comprising program instructions, wherein the program instructions are executable to:

create a block diagram on a display, wherein the block diagram implements a model of a system, wherein the block diagram comprises a plurality of interconnected nodes that visually represent functionality of the model;

generate a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram;

wherein the hardware description is useable to configure a programmable hardware element to produce a configured programmable hardware element, wherein the configured programmable hardware element implements a hardware implementation of the model; and

display one or more panels on a display for displaying output from the model during execution of the configured programmable hardware element.

42. The computer readable memory medium of claim 41,

wherein the one or more panels comprise a graphical user interface.

43. The computer readable memory medium of claim 41, wherein the program instructions are further executable to:

display one or more second panels on the display for providing input to the model during execution of the configured programmable hardware element.

44. The computer readable memory medium of claim 43, wherein the program instructions are further executable to:

receive user input to at least one of the one or more second panels during execution of the configured programmable hardware element; and

provide the user input to the configured programmable hardware element;

wherein the configured programmable hardware element adjusts operation of the model in response to the user input.

45. The computer readable memory medium of claim 41, wherein the one or more panels are created with the block diagram.

46. The computer readable memory medium of claim 41, wherein the block diagram is a data flow diagram.

47. The computer readable memory medium of claim 41, wherein the block diagram implements a model of a physical system.

48. The computer readable memory medium of claim 41,

wherein the block diagram has associated data structures which represent the block diagram;

and

wherein in generation of the hardware description, the program instructions are executable to;

traverse the data structures; and

convert the data structures into a hardware description format in response to the traversing.

49. The computer readable memory medium of claim 41, wherein the plurality of interconnected nodes includes one or more function nodes and one or more nodes representing at least one constant.

50. The computer readable memory medium of claim 41, wherein the plurality of interconnected nodes includes one or more function nodes and one or more nodes representing at least one global variable.

51. The computer readable memory medium of claim 41, wherein the plurality of interconnected nodes includes one or more function nodes and one or more nodes representing at least one input to the block diagram.

52. The computer readable memory medium of claim 41, wherein the plurality of interconnected nodes includes one or more function nodes and one or more nodes representing at least one output from the block diagram.

53. The computer readable memory medium of claim 41, wherein the plurality of interconnected nodes includes one or more function nodes and one or more nodes representing at least one sub-program.

54. The computer readable memory medium of claim 41,

wherein said generating the hardware description comprises converting each of said plurality of interconnected nodes into a hardware description format.

55. The computer readable memory medium of claim 41,

wherein the block diagram includes a plurality of nodes, wherein at least a subset of the plurality of nodes are connected to indicate data flow among the at least a subset of the plurality of nodes, wherein the plurality of nodes includes at least one node that represents control flow of data among one or more of the plurality of nodes.

56. The computer readable memory medium of claim 55,

wherein the at least one node indicates one or more of iteration, looping, and/or conditional branching for the one or more of the plurality of nodes in the block diagram.

57. The computer readable memory medium of claim 55,

wherein the at least one node indicates iteration for the one or more of the plurality of nodes in the block diagram.

58. The computer readable memory medium of claim 55,

wherein the at least one node indicates looping for the one or more of the plurality of nodes in the block diagram.

59. The computer readable memory medium of claim 55,

wherein the at least one node indicates conditional branching for the one or more of the plurality of nodes in the block diagram.

60. The computer readable memory medium of claim 55,

wherein the at least one node indicates a first portion of the block diagram, wherein the at least one node indicates one of iteration, looping or conditional branching for the first portion of the block diagram.

61. The computer readable memory medium of claim 55,

wherein the at least one node is a structure node.

62. The computer readable memory medium of claim 55,

wherein the at least one node includes an interior portion, wherein a first portion of the block diagram is comprised in the interior portion, and wherein the first portion of the block diagram comprised in the interior portion of the at least one node executes according to control flow as indicated by the at least one node.

63. The computer readable memory medium of claim 55, wherein in generating the hardware description the program instructions are executable to examine one or more node parameters associated with the at least one node and use the one or more node parameters in generating the hardware description.

64. The computer readable memory medium of claim 63, wherein the at least one node is one of an iteration node or a looping node;

wherein the at least one node includes at least one of a period parameter and a phase delay parameter, wherein the period parameter indicates a period of execution for cycles of the at least one node, and wherein the phase delay parameter indicates a phase delay of cycles of the at least one node.

65. The computer readable memory medium of claim 55, wherein the at least one node is an iteration node, wherein the iteration node indicates iteration of the one or more of the plurality of nodes in the block diagram for a plurality of times;

wherein the iteration node includes an iteration number which indicates a number of iterations for the block diagram; and

wherein said generating uses the iteration number in generating the hardware description.

66. The computer readable memory medium of claim 55, wherein the at least one node is a looping node, wherein the looping node indicates looping of the one or more of the plurality of nodes in the block diagram for a plurality of times;

wherein the looping node includes a loop condition which indicates a number of executions for the block diagram; and

wherein said generating uses the loop condition in generating the hardware description.

67. The computer readable memory medium of claim 55, wherein in generating the hardware description based on the block diagram, the program instructions are executable to convert each of said nodes into a hardware description format;

wherein, for said at least one node, the program instructions are executable to;

determine inputs and outputs to/from the at least one node;

create a hardware description of a control block which performs the control function indicated by the at least one node;

traverse input dependencies of the node; and

create a hardware description of an AND gate, including listing connections of said input dependencies of the node to said AND gate.

68. The computer readable memory medium of claim 41,

wherein in generating the hardware description based on the block diagram, the program instructions are executable to use information that is specific to a type of programmable hardware element.

69. The computer readable memory medium of claim 41,

wherein in generating the hardware description based on the block diagram, the program instructions are executable to use pre-compiled function blocks for one or more of the nodes.

70. A computer-implemented method, the method comprising:

in a computer, creating a block diagram, wherein the block diagram implements a model of a system, wherein the block diagram comprises a plurality of interconnected nodes that visually represent functionality of the model;

generating a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram;

configuring a programmable hardware element utilizing the hardware description to produce a configured programmable hardware element, wherein the configured programmable hardware element implements a hardware implementation of the model; and

displaying one or more panels on a display for displaying output from the model during execution of the configured programmable hardware element.

71. A system which generates a hardware implementation of a block diagram, the system comprising:

a computer system comprising a processor and memory, wherein the memory stores a block diagram, wherein the block diagram implements a model of a system;

wherein the memory also stores a software program which is executable to generate a hardware description based on at least a portion of the block diagram, and wherein the hardware description describes a hardware implementation of the at least a portion of the block diagram;

a device coupled to the computer system, wherein the device includes a programmable hardware element;

wherein the computer system is operable to configure the programmable hardware element utilizing the hardware description to produce a configured hardware element, and wherein the configured hardware element implements a hardware implementation of the at least a portion of the block diagram; and

a display coupled to at least one of the computer system and the device, wherein the display is operable to display one or more panels for displaying output from the model during execution of the configured programmable hardware element.

72. A computer readable memory medium comprising program instructions, wherein the program instructions are executable to:

create a block diagram on a display, wherein the block diagram represents a model of a system, wherein the block diagram comprises a plurality of interconnected nodes, wherein at least a subset of the plurality of nodes are connected to indicate data flow among the at least a subset of the plurality of nodes, wherein the plurality of nodes includes at least one node that represents control flow of data among one or more of the plurality of nodes;

generate a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram;

wherein the hardware description is useable to configure a programmable hardware element to produce a configured programmable hardware element, wherein the configured programmable hardware element implements a hardware implementation of the model.

73. The computer readable memory medium of claim 72, wherein the program instructions are further executable to:

display one or more panels on a display for displaying output from the model during execution of the configured programmable hardware element.

74. The computer readable memory medium of claim 72,

wherein the at least one node indicates one or more of iteration, looping, and/or conditional branching for the one or more of the plurality of nodes in the block diagram.

75. The computer readable memory medium of claim 72,

wherein the at least one node indicates iteration for the one or more of the plurality of nodes in the block diagram.

76. The computer readable memory medium of claim 72,

wherein the at least one node indicates looping for the one or more of the plurality of nodes in the block diagram.

77. The computer readable memory medium of claim 72,

wherein the at least one node indicates conditional branching for the one or more of the plurality of nodes in the block diagram.

78. The computer readable memory medium of claim 72,

wherein the at least one node indicates a first portion of the block diagram, wherein the at least one node indicates one of iteration, looping or conditional branching for the first portion of the block diagram.

79. The computer readable memory medium of claim 72,

wherein the at least one node is a structure node.

80. The computer readable memory medium of claim 72,

wherein the at least one node includes an interior portion, wherein a first portion of the block diagram is comprised in the interior portion, and wherein the first portion of the block diagram comprised in the interior portion of the at least one node executes according to control flow as indicated by the at least one node.

81. A system which generates a hardware implementation of a block diagram, the system comprising:

a computer system comprising a processor and memory, wherein the memory stores a block diagram, wherein the block diagram implements a model of a system, wherein the block diagram comprises a plurality of interconnected nodes, wherein at least a subset of the plurality of nodes are connected to indicate data flow among the at least a subset of the plurality of nodes, wherein the plurality of nodes includes at least one node that represents control flow of data among one or more of the plurality of nodes

wherein the memory also stores a software program which is executable to generate a hardware description based on at least a portion of the block diagram, and wherein the hardware description describes a hardware implementation of the at least a portion of the block diagram;

a device coupled to the computer system, wherein the device includes a programmable hardware element;

wherein the computer system is operable to configure the programmable hardware element utilizing the hardware description to produce a configured hardware element, and wherein the configured hardware element implements a hardware implementation of the at least a portion of the block diagram; and

a display coupled to at least one of the computer system and the device, wherein the display is operable to display one or more panels for displaying output from the model during execution of the configured programmable hardware element.