Structures for LUT-based arithmetic in PLDs

• US 7,558,812 B1
• Filed: 11/26/2003
• Issued: 07/07/2009
• Est. Priority Date: 11/26/2003
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Schleicher, Jay, Lewis, David, Cashman, David, Yuan, Jinyong, Lee, Andy L., Kim, Henry, Padalia, Ketan
• Primary Examiner(s): Ngo; Chuong D
• Application Number:
  US10/723,104
• Time in Patent Office: 2,050 Days
• Field of Search: 708/230, 708/232, 708/235, 708/320, 326/41, 326/38
• US Class Current: 708/235
• CPC Class Codes: G06F 7/575 Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A programmable logic device (PLD) includes a plurality of logic array blocks (LAB'"'"'s) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT'"'"'s can perform arithmetic efficiently, as well as non-arithmetic functions.

Claims

1. A programmable logic device (PLD) including a plurality of logic array blocks (LAB'"'"'s) connected by a PLD routing architecture, wherein at least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages, the LE comprising:

a K input look-up table (“

K-LUT”

), the K-LUT configured to input the binary input signals at respective inputs of the K-LUT and to provide, at a plurality of outputs of the K-LUT, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals;

an input line network including a network of input lines and an input multiplexer, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT, wherein the input multiplexer is configured to receive input signals from at least one of the input lines and provide output signals to the K-LUT, the input line network is configured to provide at least a first one of the input signals to both a first K-LUT portion and a second K-LUT portion in a first state, and provide a first carry-in signal to the first K-LUT portion and a second carry-in signal to the second K-LUT portion in a second state;

an output line network including a network of output lines and an output multiplexer, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture, wherein the output multiplexer selects an output signal at outputs of the K-LUT;

wherein;

the K-LUT includes a plurality of portions, each portion connected to the routing architecture via the input line network to receive at least some of the input signals;

each of the plurality of portions of the K-LUT includes circuitry to generate the binary result signals indicative of a respective separate one of the plurality of stages of the arithmetic combination of binary input signals; and

the input line network includes at least a first input multiplexer between the routing architecture and a first one of the K-LUT portions and at least a second input multiplexer between the routing architecture and a second one of the K-LUT portions;

the input line network is configured to

in-the first state, provide at least the first one of the input signals to both the first K-LUT portion and the second K-LUT portion, via the first input multiplexer and the second input multiplexer, respectively, and

in-the second state, instead provide the first carry-in signal to the first K-LUT portion and the second carry-in signal to the second K-LUT portion, via the first input multiplexer and the second input multiplexer, respectively.

2. The PLD of claim 1, wherein:

the K-LUT portions include at least a first K-LUT portion and a second K-LUT portion;

the output line network includes at least a first output multiplexer, controlled by a second one of the input signals, and at least a second output multiplexer, controlled by the second one of the input signals,

the first K-LUT portion is comprised of a first sub-portion and a second sub-portion;

the second K-LUT portion is comprised of a third sub-portion and a fourth sub-portion;

the first output multiplexer selects between the output of the first sub-portion and the second sub-portion; and

the second output multiplexer selects between the output of the third sub-portion and the fourth sub-portion.

3. The PLD of claim 2, wherein:

each of the first K-LUT portion and the second K-LUT portion is a K-1 LUT.

4. The PLD of claim 3, wherein:

each of the first sub-portion, the second sub-portion, the third sub-portion and the fourth sub-portion is a K-2 LUT.

5. The PLD of claim 2, wherein:

the output line network includes at least a third output multiplexer, controlled by a third one of the input signals; and

the third output multiplexer selects between the output of the first output multiplexer and the second output multiplexer.

6. The PLD of claim 5, wherein:

the output line network includes a fourth output multiplexer controlled by the third one of the input signals; and

the fourth output multiplexer selects between the output of the third sub-portion and the fourth sub-portion.

7. The PLD of claim 1, wherein:

the input line network includes selector circuitry configurable such that,

in a first state, each of a collection of inputs to the K-LUT that includes an input to each of the portions of the K-LUT receive a same particular binary input signal, and

in a second state, at least some of the collection of inputs to the K-LUT do not receive the particular binary input signal.

8. The PLD of claim 7, wherein:

the selector circuitry of the input line network includes a plurality of input multiplexers, the outputs of which are connected to the collection of inputs to the K-LUT, and

the input multiplexers are configurable such that, in the first state, each of the input multiplexers provides the particular binary input signal to the output of that multiplexer and, in the second state, each of at least some of the input multiplexers provides other than the particular binary input signal to the output of that multiplexer.

9. A programmable logic device (PLD) including a plurality of logic array blocks (LAB'"'"'s) connected by a PLD routing architecture, wherein at least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages, the LE comprising:

a K input look-up table (“

K-LUT”

), the K-LUT configured to input the binary input signals at respective inputs of the K-LUT and to provide, at a plurality of outputs of the K-LUT, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals;

an input line network including a network of input lines and an input multiplexer, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT, wherein the input multiplexer is configured to receive input signals from at least one of the input lines and provide output signals to the K-LUT, the input line network is configured to provide at least a first one of the input signals to both a first K-LUT portion and a second K-LUT portion in a first state, and provide a first carry-in signal to the first K-LUT portion and a second carry-in signal to the second K-LUT portion in a second state;

an output line network including a network of output lines and an output multiplexer, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture, wherein the output multiplexer selects an output signal at outputs of the K-LUT;

wherein;

the K-LUT includes a plurality of portions, each portion connected to the routing architecture via the input line network to receive at least some of the input signals;

each of the plurality of portions of the K-LUT includes circuitry to generate the binary result signals indicative of a respective separate one of the plurality of stages of the arithmetic combination of binary input signals; and

the K-LUT portions include at least a first K-LUT portion and a second K-LUT portion;

the first K-LUT portion is comprised of a first sub-portion and a second sub-portion;

the second K-LUT portion is comprised of a third sub-portion and a fourth sub-portion;

the output line network includes a multiplexer configurable to selectively provide an output from one of the third sub-portion and the fourth sub-portion, based on signal indicative of a signal output from the second sub-portion.

10. The PLD of claim 9, wherein the signal output from the second sub-portion is indicative of a carry-out of the first stage.

11. A programmable logic device (PLD) including a plurality of logic array blocks (LAB'"'"'s) connected by a PLD routing architecture, wherein at least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages, the LE comprising:

a K input look-up table (“

K-LUT”

), the K-LUT configured to input the binary input signals at respective inputs of the K-LUT and to provide, at a plurality of outputs of the K-LUT, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals;

an input line network including a network of input lines and an input multiplexer, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT, wherein the input multiplexer is configured to receive input signals from at least one of the input lines and provide output signals to the K-LUT, the input line network is configured to provide at least a first one of the input signals to both a first K-LUT portion and a second K-LUT portion in a first state, and provide a first carry-in signal to the first K-LUT portion and a second carry-in signal to the second K-LUT portion in a second state;

an output line network including a network of output lines and an output multiplexer, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture, wherein the output multiplexer selects an output signal at outputs of the K-LUT; and

at least one output multiplexer, each of the at least one output multiplexers coupled to select among signals at the outputs of the K-LUT, under the control of a carry-in signal to the LE, to provide an arithmetic output signal from the LE to an output line of the output line network.

12. A programmable logic device (PLD) including a plurality of logic array blocks (LAB'"'"'s) connected by a PLD routing architecture, wherein at least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages, the LE comprising:

a K input look-up table (LUT) (“

K-LUT”

), the K-LUT configured to input the binary input signals at respective inputs of the K-LUT and to provide, at a plurality of outputs of the K-LUT, respective binary result signals indicative of the arithmetic combination of binary input signals;

an input line network including a network of input lines and an input multiplexer, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT, wherein the input multiplexer is configured to receive input signals from at least one of the input lines;

an output line network including a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture; and

at least one output multiplexer, each of the at least one output multiplexers coupled to select among signals at the outputs of the K-LUT, under the control of a carry-in signal to the LE, to provide an arithmetic output signal from the LE to an output line of the output line network;

wherein;

the input line network includes at least a first input multiplexer between the routing architecture and a first K-LUT portion and at least a second input multiplexer between the routing architecture and a second K-LUT portion;

the input line network is configured to

in a first state, provide at least a first one of the input signals to both the first K-LUT portion and the second K-LUT portion, via the first input multiplexer and the second input multiplexer, respectively, and

in a-second state, instead provide a first carry-in signal to the first K-LUT portion and a second carry-in signal to the second K-LUT portion, via the first input multiplexer and the second input multiplexer, respectively.