System and method for register renaming

• US 7,558,945 B2
• Filed: 09/27/2005
• Issued: 07/07/2009
• Est. Priority Date: 12/31/1992
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Garg, Sanjiv, Iadonato, Kevin R., Deosaran, Trevor A.
• Primary Examiner(s): Treat; William M
• Application Number:
  US11/235,090
• Publication Number:
  US 20060020773A1
• Time in Patent Office: 1,379 Days
• Field of Search: 712/217
• US Class Current: 712/217
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.

Claims

1. A system for renaming source registers of instructions to be executed in a microprocessor, the system comprising:

an instruction window comprising a plurality of storage locations each of which stores a single instruction that may be issued during a single processor cycle, wherein only a subset of the plurality of storage locations may be filled with new instructions in a single processor cycle; and

a plurality of register renaming circuits, wherein each of the plurality of register renaming circuits is uniquely associated with a storage location in the subset of the plurality of storage locations and configured to determine if a new instruction stored in the corresponding storage location is dependent on any older instructions in the instruction window and to output a renamed source register address for the new instruction if such a dependency exists.

2. The system of claim 1, further comprising:

control logic that assigns one of a plurality of tags to a new instruction in the instruction window, each of the plurality of tags uniquely identifying a register for storing a result corresponding to an instruction in the instruction window.

3. The system of claim 2, further comprising:

a first-in-first-out (FIFO) buffer that stores the plurality of tags;

wherein the control logic assigns a tag from the head of the FIFO buffer to the new instruction in the instruction window.

4. The system of claim 3, wherein the FIFO buffer includes:

a plurality of slots equal in number to a predetermined size of the instruction window, each of the plurality of slots containing a unique one of the plurality of tags, wherein an order defined by positions of the plurality of tags in the FIFO buffer corresponds to an order of instructions in the instruction window.

5. The system of claim 2, wherein each of the plurality of register renaming circuits includes:

a data dependency checker that determines if the new instruction in the instruction window is dependent on an older instruction in the instruction window by comparing a source register address of the new instruction in the instruction window with a destination register address of the older instruction in the instruction window.

6. The system of claim 5, wherein the data dependency checker comprises:

a compare circuit that compares the source register address of the new instruction in the instruction window with the destination register address of the older instruction in the instruction window.

7. The system of claim 5, wherein each of the plurality of register renaming circuits further comprises:

tag assignment logic that outputs a renamed source register address for the new instruction in the instruction window, wherein the renamed source register address comprises a tag assigned to the older instruction in the instruction window if the new instruction in the instruction window is dependent on the older instruction in the instruction window.

8. The system of claim 7, further comprising:

a register file that stores a source register address and a destination register address for each instruction in the instruction window, the register file coupled to the data dependency checker for providing the source register address of the new instruction in the instruction window and the destination register address of the older instruction in the instruction window to the data dependency checker.

9. The system of claim 7, further comprising:

a register file comprising a write data port and a write address port;

wherein the tag assignment logic stores the renamed source register address in the register file by providing the renamed source register address to the write data port and by providing the tag assigned to the older instruction in the instruction window to the write address port if the new instruction in the instruction window is dependent on the older instruction in the instruction window.

10. The system of claim 9, wherein the register file further comprises:

a read data port and a read address port;

wherein the renamed source register address stored in the register file is accessed on the read data port by providing the tag associated with the new instruction in the instruction window to the read address port.

11. The system of claim 7, further comprising:

a retirement unit that determines whether the new instruction in the instruction window has retired.

12. The system of claim 11, further comprising:

logic that selects one of the register source address of the new instruction in the instruction window or the renamed register source address based on whether the new instruction in the instruction window has retired.

13. A computer system, comprising:

a memory unit;

a bus coupled to the memory unit for retrieving program instructions therefrom; and

a processor coupled to the bus, wherein the process comprises a register renaming system that includes;

an instruction window comprising a plurality of storage locations each of which stores a single program instruction that may be issued during a single processor cycle, wherein only a subset of the plurality of storage locations may be filled with new program instructions retrieved from the memory unit in a single processor cycle; and

a plurality of register renaming circuits, wherein each of the plurality of register renaming circuits is uniquely associated with a storage location in the subset of the plurality of storage locations and configured to determine if a new program instruction stored in the corresponding storage location is dependent on any older program instructions in the instruction window and to output a renamed source register address for the new program instruction if such a dependency exists.

14. The computer system of claim 13, wherein the register renaming system further comprises:

control logic that assigns one of a plurality of tags to a new program instruction in the instruction window, each of the plurality of tags uniquely identifying a register for storing a result corresponding to a program instruction in the instruction window.

15. The computer system of claim 14, wherein the register renaming system further comprises:

a first-in-first-out (FIFO) buffer that stores the plurality of tags;

wherein the control logic assigns a tag from the head of the FIFO buffer to the new program instruction in the instruction window.

16. The computer system of claim 15, wherein the FIFO buffer includes:

a plurality of slots equal in number to a predetermined size of the instruction window, each of the plurality of slots containing a unique one of the plurality of tags, wherein an order defined by positions of the plurality of tags in the FIFO buffer corresponds to an order of program instructions in the instruction window.

17. The computer system of claim 14, wherein each of the plurality of register renaming circuits includes:

a data dependency checker that determines if the new program instruction in the instruction window is dependent on an older program instruction in the instruction window by comparing a source register address of the new program instruction in the instruction window with a destination register address of the older program instruction in the instruction window.

18. The computer system of claim 17, wherein the data dependency checker comprises:

a compare circuit that compares the source register address of the new program instruction in the instruction window with the destination register address of the older program instruction in the instruction window.

19. The computer system of claim 17, wherein each of the plurality of register renaming circuits further comprises:

tag assignment logic that outputs a renamed source register address for the new instruction in the instruction window, wherein the renamed source register address comprises a tag assigned to the older instruction in the instruction window if the new instruction in the instruction window is dependent on the older instruction in the instruction window.

20. The computer system of claim 19, further comprising:

a register file that stores a source register address and a destination register address for each program instruction in the instruction window, the register file coupled to the data dependency checker for providing the source register address of the new program instruction in the instruction window and the destination register address of the older program instruction in the instruction window to the data dependency checker.

21. The computer system of claim 19, wherein the register renaming system further comprises:

a register file comprising a write data port and a write address port;

wherein the tag assignment logic stores the renamed source register address in the register file by providing the renamed source register address to the write data port and by providing the tag assigned to the older program instruction in the instruction window to the write address port if the new program instruction in the instruction window is dependent on the older instruction in the instruction window.

22. The computer system of claim 21, wherein the register file further comprises:

a read data port and a read address port;

wherein the renamed source register address stored in the register file is accessed on the read data port by providing the tag associated with the new program instruction in the instruction window to the read address port.

23. The computer system of claim 19, wherein the register renaming system further comprises:

a retirement unit that determines whether the new program instruction in the instruction window has retired.

24. The computer system of claim 23, wherein the register renaming system further comprises:

logic that selects one of the register source address of the new program instruction in the instruction window or the renamed register source address based on whether the new program instruction in the instruction window has retired.