Methods for determining simultaneous switching induced data output timing skew

• US 7,558,979 B2
• Filed: 08/01/2005
• Issued: 07/07/2009
• Est. Priority Date: 10/23/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Kwang-il, Jang, Seong-jin, Song, Ho-young
• Primary Examiner(s): Lee; Thomas
• Assistant Examiner(s): Brown; Michael J
• Application Number:
  US11/194,180
• Publication Number:
  US 20060092717A1
• Time in Patent Office: 1,436 Days
• Field of Search: 713/500, 713/501, 713/503, 370/508
• US Class Current: 713/500
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device. The memory device is read to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device. Timing skew is determined between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device.

Claims

1. A data training method performed in a memory device which does not include an additional device for data training, the method comprising:

(a) writing a predetermined data pattern to the memory device;

(b) reading a data pattern from the memory device; and

(c) determining a delay time in data transmission by measuring a delay time between the read data pattern and the predetermined data pattern,

wherein a speed at which the predetermined data pattern is written to the memory device is less than a normal operating speed of the memory device, and

wherein (b) the reading of the data pattern comprises;

(b1) operating the memory device at the normal operating frequency; and

(b2) reading the data pattern from the memory device at the normal operating frequency; and

wherein (b) the reading of the data pattern further comprises (b3) selecting a pin of the memory device which performs the data training.

2. The data training method of claim 1, wherein (a) the writing of the predetermined data pattern comprises:

(a1) operating the memory device at a frequency less than a normal operating frequency of the memory device; and

(a2) writing the predetermined data pattern to a predetermined cell of the memory device.

3. The data training method of claim 1, wherein (b) the reading of the data pattern further comprises (b3) setting a minimum delay time in data transmission.

4. The data training method of claim 3, wherein (c) the determining of the delay time in data transmission comprises:

(c1) measuring a delay time between the read data pattern and the predetermined data pattern;

(c2) determining the delay time in data transmission using the measured delay time and the minimum delay time; and

(c3) storing the determined delay time, and selecting another pin of the memory device when it is determined that all pins of the memory device are not checked.