Apparatus and method for test and debug of a processor/core having advanced power management

• US 7,558,984 B2
• Filed: 04/26/2006
• Issued: 07/07/2009
• Est. Priority Date: 04/27/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: McGowan, Robert A.
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US11/411,381
• Publication Number:
  US 20060248394A1
• Time in Patent Office: 1,168 Days
• Field of Search: 714 30- 34, 714/724, 714733-734
• US Class Current: 714/31
• CPC Class Codes: G06F 11/2242 in multi-processor systems, e.g. one processor becoming the test master G06F11/2736 takes precedence

Abstract

An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. When the processor/cores have advanced power management systems, a sleep inhibit signal can be applied to the processor/core state machine preventing the state machine from entering a lower power state. The parameters of the processor/core can be tested to determine when the test and debug procedures can be implemented. When the (power) parameters are to low to permit test and debug, the test and debug unit can provide a command forcing the state machine into a state for which test and debug procedures can be implemented.

Claims

1. An apparatus for preventing a power-down of a selected processor/core, the apparatus comprising:

a test and debug unit, the test and debug unit generating a test and debug command requesting a sleep-inhibit signal for a selected processor/core;

a plurality of processor/cores, each processor/core coupled to a power state machine responsive to a sleep-inhibit signal, preventing a decrease in power to the associated processor/core; and

an interface unit providing an interface between the test and debug unit and the processor/cores, the interface unit comprising a test access port (TAP) unit and a logic unit, the TAP transferring the test and debug command to the logic unit, the logic unit translating the test and debug command to the sleep-inhibit signal, and the interface unit applying the sleep-inhibit signal to the power state machine of the selected processor/core.

2. The apparatus as recited in claim 1 wherein the sleep-inhibit signal does not prevent transitions to lower power already in progress.

3. The apparatus as recited in claim 1 further including a register unit coupled to the logic unit for storing parameters resulting from the state of the power state machine.

4. The apparatus as recited in claim 3 wherein, after the sleep inhibit signal has been applied to the power state machine, the parameters associated with the power state machine stored in the register unit are transferred to the test and debug unit.

5. The apparatus as recited in claim 4 wherein the power state machine controls at least one parameter selected from the group consisting of power parameters and clock parameters.

6. A method for facilitating the test and debug of a plurality of processor/cores, wherein each processor/core comprises a test access port (TAP). the method comprising:

receiving a test command from a test and debug unit in a TAP of an interface unit coupled to the TAPs of the plurality of processors/cores, wherein the test command requests a sleep-inhibit signal for a selected processor/core;

translating the test command to the sleep-inhibit signal. wherein the translating is performed by a logic unit in the interface unit; and

applying the sleep inhibit signal to a power state machine coupled to the selected processor/core, the sleep-inhibit signal preventing a decrease in power to the selected processor/core.

7. The method as recited in claim 6 further comprising:

after applying the sleep-inhibit signal, testing the selected processor/core to determine whether parameters permit the selected processor/core to be tested.

8. The method as recited in claim 7 further comprising:

when the processor/core parameters do not permit testing the processor/core, forcing the parameters of the selected processor/core to a level wherein the selected processor/core can be tested.

9. The method as recited in claim 8 wherein the forcing includes applying control signals from the logic unit to the power state machine.

10. The method as recited in claim 9 wherein the forcing includes controlling at least one parameter selected from a group consisting of a power parameter and a clock parameter.

11. An apparatus for test and debug of a processor/core having an advanced power management system, the apparatus comprising:

a test and debug unit for generating test and debug commands;

a logic unit;

an interface TAP unit, the interface TAP unit providing an interface between the test and debug unit and the logic unit, wherein the logic unit can translate test and debug commands into control signals, one of the control signals being a sleep-inhibit signal; and

a state machine coupled to the processor/core the state machine controlling the power of the processor/core by states controlling at least one of the power and the clock parameters, wherein the application of the sleep-inhibit signal to the state machine prevents the state machine from transitioning to a lower power.

12. The apparatus as recited in claim 11 further comprising a register unit, the register unit storing parameters associated with the processor/core, after application of the sleep-inhibit signal, the parameters associated with the processor/core are transferred to the test and debug unit to determine whether the parameters permit the test and debug of the processor/core, the test and debug unit generating a force command when the parameters do not permit the test and debug procedures, the force command translated by the logic unit, the logic unit applying force control signals resulting in parameters in the processor/core that permit test and debug.

13. An apparatus comprising:

a processor/core comprising a processor test access port (TAP), wherein the processor TAP is operable to control testing of the processor/core;

a power state machine controllably coupled to the processor/core to change a power parameter of the processor/core to prevent a decrease in power to the processor/core responsive to a sleep-inhibit signal; and

an interface unit controllably coupled to the power state machine, wherein the interface unit comprises an interface TAP operable to receive a test command requesting the sleep-inhibit signal for the processor/core, and wherein the interface unit is operable to apply the sleep-inhibit signal to the power state machine.

14. The apparatus as recited in claim 13 wherein the interface unit further comprises a register unit for storing parameters of the power state machine.

15. The apparatus as recited in claim 13 wherein the interface unit further comprises a logic unit operable to translate the test command to the sleep-inhibit signal.

16. The apparatus as recited in claim 14 wherein the interface unit is further operable to provide the parameters to a test and debug unit.