Low voltage signal stripping circuit for an RFID reader

• US 7,559,477 B2
• Filed: 09/08/2006
• Issued: 07/14/2009
• Est. Priority Date: 12/05/2003
• Status: Active Grant

• Current Assignee: Assa Abloy AB
• Original Assignee: Assa Abloy AB
• Inventors: Steffen, Dale A.
• Primary Examiner(s): TRAIL, ALLYSON NEEL
• Application Number:
  US11/518,060
• Publication Number:
  US 20070001008A1
• Time in Patent Office: 1,040 Days
• Field of Search: 340/10.1, 340/572.1, 340/572.7, 340/573.1, 340/834, 340/10.3, 340/10.4, 340/572.4, 235/472.01, 235/451, 343/701, 343/742, 343/867, 455/41.2
• US Class Current: 235/472.01
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer

Abstract

A reader of an RFID system has excitation circuitry for generating a higher voltage excitation signal, receiving circuitry for reading a lower voltage transponder signal and an antenna coupled with the excitation circuitry for transmitting the excitation signal and coupled with the receiving circuitry for receiving the transponder signal. The receiving circuitry includes a low voltage signal stripping circuit coupled with the antenna for isolating the transponder signal from the excitation signal preliminary to the receiving circuitry reading the transponder signal. The bulk of the components of the low voltage signal stripping circuit are low voltage components, which can be included in an application specific integrated circuit.

Claims

1. A method for processing a high voltage antenna signal waveform comprising the steps of:

providing a high voltage antenna signal waveform including a low voltage transponder signal containing readable information superposed on a high voltage excitation signal;

specifying a location on said waveform where a waveform portion is to be isolated;

specifying a size of said waveform portion to be isolated at said specified location on said waveform;

isolating said waveform portion, wherein said waveform portion contains said readable information; and

reading said readable information on said waveform portion.

2. The method of claim 1, wherein said location is specified by specifying a relative voltage value on said waveform.

3. The method of claim 1, wherein said size of said waveform portion is specified by specifying an absolute voltage range applied to said waveform at said specified location.

4. A method for processing a high voltage antenna signal comprising the steps of:

receiving a high voltage antenna signal containing readable information from an antenna at an input of a low voltage stripping circuit;

limiting a voltage of said high voltage antenna signal to create a low voltage output signal containing said readable information;

creating a DC shift voltage or a DC shift current;

selectively distributing a feedback signal from an amplifier having an output operating range; and

creating a summed signal containing said readable information by summing said low voltage output signal, said selectively distributed feedback signal, and said DC shift voltage or said DC shift current.

5. The method of claim 4, wherein said high voltage antenna signal has a voltage exceeding an upper voltage tolerance of said amplifier.

6. The method of claim 4, wherein said low voltage output signal has a voltage below an upper voltage tolerance of said amplifier.

7. The method of claim 4, wherein said voltage of said high voltage antenna signal is limited by passing said high voltage antenna signal through an inlet resistor.

8. The method of claim 4, wherein said amplifier has a first input and a second input held to a substantially matching voltage value, wherein said summed signal is input to said first input and a voltage reference is input to said second input.

9. The method of claim 4, wherein said amplifier has an inverting input and a non-inverting input held to a substantially matching voltage value, wherein said summed signal is input to said inverting input and a voltage reference is input to said non-inverting input.

10. The method of claim 4, wherein said amplifier provides a gain to said summed signal varying as a function of a voltage of said feedback signal distributed to said summed signal, said gain being reduced when said voltage of said feedback signal distributed to said summed signal is outside said predetermined voltage range.

11. The method of claim 4 further comprising passing said summed signal through said amplifier to create an amplifier output signal containing said readable information.

12. The method of claim 11, wherein said amplifier provides a gain to said summed signal in response to said selectively distributed feedback signal to create said amplifier output signal.

13. The method of claim 11 further comprising reading said readable information on said amplifier output signal.

14. A method for processing a high voltage antenna signal comprising the steps of:

receiving a high voltage antenna signal containing readable information from an antenna at an input of a low voltage stripping circuit;

limiting a voltage of said high voltage antenna signal to create a low voltage output signal containing said readable information;

creating a DC shift voltage or a DC shift current;

selectively distributing a feedback signal from an amplifier having an output operating range, wherein said feedback signal is selectively distributed by a feedback circuit having a first pathway with a low impedance to said feedback signal when a voltage of said feedback signal is above an upper limit of a predetermined voltage range, a second pathway with a low impedance to said feedback signal when said voltage of said feedback signal is below a lower limit of said predetermined voltage range, and a third pathway with a low impedance to said feedback signal when a voltage of said feedback signal is within said predetermined voltage range; and

creating a summed signal containing said readable information by summing said low voltage output signal, said selectively distributed feedback signal, and said DC shift voltage or said DC shift current.

15. The method of claim 14 further comprising passing said summed signal through said amplifier to create an amplifier output signal containing said readable information.

16. The method of claim 15, wherein said amplifier provides a gain to said summed signal in response to said selectively distributed feedback signal to create said amplifier output signal.

17. The method of claim 15 further comprising reading said readable information on said amplifier output signal.

18. The method of claim 14, wherein said amplifier has a first input and a second input held to a substantially matching voltage value, wherein said summed signal is input to said first input and a voltage reference is input to said second input.

19. The method of claim 14, wherein said amplifier has an inverting input and a non-inverting input held to a substantially matching voltage value, wherein said summed signal is input to said inverting input and a voltage reference is input to said non-inverting input.

20. The method of claim 14, wherein said amplifier provides a gain to said summed signal varying as a function of a voltage of said feedback signal distributed to said summed signal, said gain being reduced when said voltage of said feedback signal distributed to said summed signal is outside said predetermined voltage range.