Semiconductor constructions and semiconductor device fabrication methods

• US 7,560,310 B2
• Filed: 12/27/2007
• Issued: 07/14/2009
• Est. Priority Date: 02/03/2006
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Mandelman, Jack Allan, Joshi, Rajiv V., Hsu, Louis L. C.
• Primary Examiner(s): Ghyka; Alexander G
• Assistant Examiner(s): Roman; Angel
• Application Number:
  US11/965,445
• Publication Number:
  US 20080105969A1
• Time in Patent Office: 565 Days
• Field of Search: 438/106, 438/123, 257/E21.001
• US Class Current: 438/122
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/10158 at the passive surface
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/96 Porous semiconductor
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.

Claims

1. A method of fabricating a semiconductor device, comprising:

etching a substrate formed on a backside of a semiconductor wafer to form a recess in said substrate; and

forming a sputter film in said recess, said sputter film including;

a first layer comprising a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of said substrate;

a second layer formed on said first layer and comprising a second material having a thermal conductivity which is greater than a thermal conductivity of said substrate; and

a transition layer which is formed between said first and second layers and comprises said first and second materials.

2. The method of claim 1, wherein said transition layer gradually transition from a first end in which a content of said first material is greater than a content of said second material, to a second end in which a content of said first material is greater than a content of said second material, to a second end in which a content of said first material is less than a content of said second material.

3. The method of claim 2, wherein said substrate comprises a silicon substrate, said first layer comprises a silicon layer, and said second layer comprises an aluminum layer.

4. The method of claim 3, wherein said first layer is formed in said recess directly on said silicon substrate.

5. The method of claim 1, further comprising:

mounting a heat sink on said sputter film.

6. The method of claim 5, wherein said heat sink has a CTE which is at least substantially equal to a CTE of said second material.

7. The method of claim 1, wherein said first material comprises a semiconductor and said second material comprises a metal.

8. The method of claim 1, wherein said first material comprises silicon and said second material comprises aluminum.

9. The method of claim 1, wherein said wafer includes a silicon-on-insulator wafer including a buried insulating layer.

10. The method of claim 1, further comprising:

forming a barrier layer on a backside of said buried insulating layer,

wherein a thickness of a frontside of said wafer between an uppermost surface of said wafer and said barrier layer is in a range from about 10 to about 20% of a total thickness of said wafer.

11. The method of claim 1, wherein said coefficient of thermal expansion (CTE) of said first material is equal to said CTE of said substrate.

12. The method of claim 1, wherein said wafer comprises a silicon-on-insulator wafer and said first material comprises silicon.

13. The method of claim 1, wherein a thickness of said sputter film is substantially equal to a thickness of said recess in said substrate.

14. A method of fabricating a semiconductor device, comprising:

etching a silicon substrate formed on a backside of a silicon-on-insulator (SOI) wafer to form a recess in said substrate;

forming a sputter film in said recess, said sputter film including;

a first layer formed directly on said silicon substrate and comprising silicon;

a second layer formed on said first layer and comprising a metal; and

a transition layer which is formed between said first and second layers and comprises silicon and said metal, said transition layer gradually transitioning from a first end in which a content of silicon is greater than a content of said metal, to a second end in which a content of silicon is less than a content of said metal; and

mounting a heat sink on said sputter film, said heat sink having a CTE which is at least substantially equal to a CTE of said metal.

15. The method of claim 14, further comprising:

forming a barrier layer on a backside of a buried insulating layer of a silicon-on-insulator (SOI) wafer, a thickness of a frontside of said wafer between an uppermost surface of said wafer and said baffler layer being in a range from about 10 to about 20% of a total thickness of said wafer.