Robust leaded molded packages and methods for forming the same

• US 7,560,311 B2
• Filed: 06/01/2006
• Issued: 07/14/2009
• Est. Priority Date: 04/16/2002
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Cabahug, Elsie Agdon, Tumulak-Rios, Margie Sebial, Manatad, Romel N., Montayre, Lilith U., Gestole, Marvin Rosalejos
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US11/446,342
• Publication Number:
  US 20060231933A1
• Time in Patent Office: 1,139 Days
• Field of Search: 257/666, 257/787, 257/728, 257672-676, 438/123, 438/611
• US Class Current: 438/123
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.

Claims

1. A method for forming a semiconductor package, the method comprising:

(a) providing a plurality of leadframe structures in a leadframe carrier comprising a saw guide slot, wherein the leadframe carrier comprises a plurality of leadframe structures, each leadframe structure comprising (i) a die attach region, and (ii) a plurality of leads extending away from the die attach region;

(b) attaching semiconductor dies to the die attach regions, wherein a plurality of solder structures is between each semiconductor die and each die attach region;

(c) molding a molding material around at least a portion of each semiconductor die and at least a portion of each die attach region; and

(d) cutting the leadframe carrier with a saw using the saw guide slot.

2. The method of claim 1 wherein the leadframe carrier is on a jig including vacuum holes.

3. The method of claim 1 further comprising depositing solder paste on the die attach regions, and wherein each of the semiconductor dies is bumped with high lead solder bumps.

4. The method of claim 1 wherein each semiconductor die comprises a first side and a second side, and wherein after (d), the molded molding material covers the first side of the semiconductor die and exposes the second side of the semiconductor die.

5. The method of claim 1 wherein each of the plurality of leadframe structures comprises a layer of metal plating.

6. The method of claim 1 further comprising forming a solder deposit on each of the die attach regions of the leadframe structures after (a) and before (b).

7. The method of claim 1 wherein the molding material comprises an epoxy molding compound.

8. The method of claim 1 wherein (c) molding comprises using a film assisted molding process.

9. The method of claim 1 wherein each leadframe structure includes a plurality of depressions, each depression being between a die attach region and a lead.

10. The method of claim 1 wherein each die attach region of each leadframe structure comprises a slot.

11. A method for forming a semiconductor package, the method comprising:

(a) providing a leadframe structure comprising (i) a die attach region comprising an aperture, and (ii) a plurality of leads extending away from the die attach region;

(b) attaching a semiconductor die to the die attach region, wherein the semiconductor die comprises a first side, a second side, a bond pad having a first uneven surface at the first side, and an underbump metallurgy layer having a second uneven surface on the first uneven surface of the bond pad, and wherein a plurality of solder structures is between the semiconductor die and the die attach region, and a solder structure in the plurality of solder structures contacts the second uneven surface;

(c) reflowing the plurality of solder structures; and

(d) molding a molding material around at least a portion of the semiconductor die and at least a portion of each die attach region, wherein the molding material passes through the aperture in the die attach region.

12. The method of claim 11 wherein the molding material exposes the second side of the semiconductor die and covers the first side of the semiconductor die.

13. The method of claim 11 wherein the semiconductor die comprises a vertical transistor.

14. A method for forming a semiconductor package, the method comprising:

(a) providing a leadframe structure comprising (i) a die attach region comprising edge regions and an aperture, (ii) a plurality of leads comprising inner portions attached to the edge regions and extending away from the die attach region, and (iii) a plurality of depressions respectively formed in the edge regions proximate the inner portions of the leads;

(b) attaching a semiconductor die to the die attach region, wherein the semiconductor die comprises a first side, a second side, and a bond pad at the first side, and wherein a plurality of solder structures is between the semiconductor die and the die attach region;

(c) reflowing the plurality of solder structures; and

(d) molding a molding material around at least a portion of the semiconductor die and at least a portion of each die attach region, wherein the molding material passes through the aperture in the die attach region,

wherein the edge regions are configured to restrict the flow of the solder structures towards the leads during reflowing.

15. The method of claim 14 wherein the molding material exposes the second side of the semiconductor die and covers the first side of the semiconductor die.

16. The method of claim 14 wherein the semiconductor die comprises a vertical transistor.

17. A method for forming a semiconductor package, the method comprising:

(a) providing a leadframe structure comprising (i) a die attach region comprising edge regions, (ii) a plurality of leads comprising inner portions attached to the edge regions and extending away from the die attach region, and (iii) a plurality of depressions respectively formed in the edge regions proximate the inner portions of the leads;

(b) attaching a semiconductor die to the die attach region, wherein the semiconductor die comprises a first side, a second side, and a bond pad having an uneven surface at the first side, and wherein a plurality of solder structures is between the semiconductor die and the die attach region;

(c) reflowing the plurality of solder structures; and

(d) molding a molding material around at least a portion of the semiconductor die and at least a portion of each die attach region

wherein the edge regions are configured to restrict the flow of the solder structures towards the leads during reflowing.

18. The method of claim 17 wherein the molding material exposes the second side of the semiconductor die and covers the first side of the semiconductor die.

19. The method of claim 17 wherein the semiconductor die comprises a vertical transistor.

20. The method of claim 17 wherein the semiconductor die comprises an LDMOS.

21. The method of claim 17 wherein the molding material is an epoxy molding material.

22. The method of claim 21 wherein the semiconductor die comprises a vertical power MOSFET.

23. The method of claim 17 wherein the semiconductor die comprises a vertical power MOSFET.

24. The method of claim 17 wherein the leadframe structure is pre-plated.

25. The method of claim 17 wherein the semiconductor die comprises a source region and a gate region.