Strained Si on multiple materials for bulk or SOI substrates

• US 7,560,328 B2
• Filed: 03/30/2007
• Issued: 07/14/2009
• Est. Priority Date: 06/03/2004
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Zhu, Huilong, Dokumaci, Omer H., Gluschenkov, Oleg G.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US11/694,373
• Publication Number:
  US 20070166897A1
• Time in Patent Office: 837 Days
• Field of Search: 438/199, 438/218, 438/285, 438/494, 438/FOR.191, 257/E21.618
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrates a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.

Claims

1. A method of forming a semiconducting substrate comprising:

providing a Si-containing substrate;

forming a first pad stack atop a first portion of said Si-containing substrate, said first pad stack comprising a compressive layer positioned atop said first portion of said Si-containing substrate, a first semiconducting layer atop said compressive layer and a first etch barrier atop said first semiconducting layer;

forming a second pad stack atop a second portion of said Si-containing substrate, said second pad stack comprising a tensile layer positioned atop said second portion of said Si-containing substrate, a second semiconducting layer atop said tensile layer, and a second etch baffler atop said second semiconducting layer;

etching said Si-containing substrate selective to said first etch barrier and said second etch baffler, wherein said compressive layer elastically transfers a tensile strain to said first semiconducting layer and said tensile layer elastically transfers a compressive strain to said second semiconducting layer;

removing said first etch baffler and said second etch barrier; and

forming an isolation region between said first pad stack and said second pad stack, said isolation region having an upper surface that is substantially coplanar to an upper surface of said first semiconducting layer and to an upper surface of said second semiconducting layer.

2. The method of claim 1, wherein said compressive layer comprises SiGe.

3. The method of claim 2, wherein said SiGe comprises Ge present in a concentration ranging from about 5% to about 30% by atomic weight percent.

4. The method of claim 1, wherein said tensile layer comprises Si:

C, wherein said Si;

C comprises carbon present in a concentration of less than about 6 % by atomic weight percent.

5. The method of claim 2 wherein forming said first pad stack further comprises:

epitaxially growing SiGe atop said Si-containing substrate, wherein said SiGe is grown to a thickness which is less than a SiGe critical thickness;

epitaxially growing said first semiconducting layer atop said SiGe, wherein said first semiconducting layer has a thickness which is less than a first semiconducting layer critical thickness; and

depositing said first etch barrier, where said first etch baffler comprises a dielectric.

6. The method of claim 5 wherein said SiGe critical thickness is a dimension at which said SiGe layer is in compression.

7. The method of claim 5 wherein said SiGe critical thickness and said semiconducting layer critical thickness is a maximum dimension under which defects formed within said SiGe and said first semiconducting layer are less than 1.0×

10⁵ cm<sup>−

2</sup>.

8. The method of claim 4 wherein forming said second pad stack further comprises:

epitaxially growing Si;

C atop said Si-containing substrate, wherein said Si;

C is grown to a thickness which is less than a Si;

C critical thickness;

epitaxially growing said first semiconducting layer atop said Si;

C, wherein said first semiconducting layer has a thickness which is less than a first semiconducting layer critical thickness; and

depositing said first etch baffler, wherein said first etch baffler comprises a dielectric.

9. The method of claim 7 wherein said Sit critical thickness is a dimension at which said Si:

C layer is in tension.

10. The method of claim 7 wherein said Si:

C critical thickness and said semiconducting layer critical thickness is a maximum dimension under which defects formed within said Si;

C layer and said first semiconducting layer are less than 1.0×

10⁵ cm<sup>−

2</sup>.

11. The method of claim 1 further comprising forming at least one nFET device on said upper surface of said first semiconducting layer and forming at least one pFET device on said upper surface of said second semiconducting layer, wherein source/drain regions of said at least one nFET device are located within said first semiconducting layer and source/drain regions of said at least one pFET device are located within said second semiconducting layer.