Method for forming a silicided gate

• US 7,560,331 B2
• Filed: 02/14/2006
• Issued: 07/14/2009
• Est. Priority Date: 07/28/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Seok-Woo, Kim, Hyun-Su, Yun, Jong-Ho, Jung, Eun-Ji, Lee, Sang-Woo
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): SCARLETT, SHAKA S
• Application Number:
  US11/354,748
• Publication Number:
  US 20070026578A1
• Time in Patent Office: 1,246 Days
• Field of Search: None
• US Class Current: 438/230
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A gate is silicided through its sides while limiting silicidation through the top of the gate. A blocking layer may be formed over the gate layer, and the sidewalls of the gate layer are exposed. A layer of metal is formed on the sidewalls of the gate and thermally treated to silicide the gate layer. The sidewalls of the gate maybe exposed through an etching process in which a silicide layer formed over the blocking layer is used as an etch mask.

Claims

1. A method comprising:

forming a gate layer over a semiconductor substrate;

forming a blocking layer to cover a top of the gate layer;

exposing sidewalls of the gate layer; and

siliciding the gate layer through the sidewalls of the gate layer;

where the gate layer is substantially fully silicided by a single layer of metal; and

where the blocking layer comprises silicon nitride.

2. The method of claim 1 where the blocking layer is formed to a thickness of about 300 to about 1000 angstroms.

3. The method of claim 1 where exposing sidewalls of the gate layer comprises exposing at least half of the height of the gate layer.

4. A method comprising:

forming a gate layer over a semiconductor substrate;

forming a blocking layer to cover a top of the gate layer;

exposing sidewalls of the gate layer; and

siliciding the gate layer through the sidewalls of the gate layer;

where exposing the sidewalls comprises;

forming a suicide layer over the blocking layer; and

using the silicide layer as an etching mask.

5. The method of claim 4 where forming the silicide layer over the blocking layer comprises:

forming a polysilicon layer over the blocking layer; and

siliciding the polysilicon layer.

6. The method of claim 5 where the blocking layer comprises silicon nitride.

7. A method comprising:

forming a gate layer over a semiconductor substrate;

forming a blocking layer to cover a top of the gate layer;

exposing sidewalls of the gate layer;

siliciding the gate layer through the sidewalls of the gate layer;

forming active regions in the semiconductor substrate at either side of the gate structure; and

forming a second blocking layer over the active regions;

where the gate layer is substantially fully silicided by a single layer of metal.

8. The method of claim 7 where forming the second blocking layer comprises:

forming spacers on sidewalls of the gate layer;

forming an interdielectric layer over the active regions; and

etching a portion of the spacers and interdielectric layer.

9. A method comprising:

forming a gate layer over a semiconductor substrate;

forming a blocking layer to cover a top of the gate layer;

exposing sidewalls of the gate layer; and

siliciding the gate layer through the sidewalls of the gate layer;

where the gate layer is substantially fully silicided by a single layer of metal; and

where siliciding the gate layer through the sidewalls of the gate layer comprises;

forming a metal layer over the blocking layer and exposed sidewalls of the gate layer; and

thermally treating the gate layer and the metal layer.

10. The method of claim 9 where the metal layer comprises nickel.

11. A method comprising:

forming a gate layer over a channel region for a transistor;

siliciding the gate layer through sidewalls of the gate layer; and

preventing silicidation through a top of the gate layer;

where the gate layer is substantially fully silicided by a single layer of metal.

12. The method of claim 11 where limiting silicidation through the top of the gate layer comprises forming a blocking layer over the gate layer.

13. The method of claim 12 where the blocking layer comprises silicon nitride.

14. The method of claim 13 where the blocking layer is formed to a thickness of about 300 to about 1000 angstroms.

15. A method comprising:

forming a gate layer over a channel region for a transistor;

siliciding the gate layer through sidewalls of the gate layer;

limiting silicidation through a top of the gate layer, including forming a blocking layer over the gate layer; and

forming a silicide layer over the blocking layer.

16. The method of claim 15 further comprising using the silicide layer as an etching mask to expose the sidewalls of the gate layer.

17. The method of claim 15 where forming the suicide layer over the blocking layer comprises:

forming a polysilicon layer over the blocking layer; and

siliciding the polysilicon layer.

18. A method for forming a gate structure comprising:

a step for forming a gate layer over a semiconductor substrate;

a step for siliciding the gate layer; and

a step for preventing siliciding at the top of the gate layer;

where the gate layer is substantially fully silicided by a single layer of metal.

19. The method of claim 18 where the step for siliciding the gate layer comprises a step for siliciding the gate layer through sidewalls of the gate layer.

20. The method of claim 18 where the step for preventing siliciding at the top of the gate layer comprises a step for blocking a metal layer from contacting the top of the gate layer.

21. The method of claim 20 where the step for blocking a metal layer from contacting the top of the gate layer comprises forming a blocking layer over the gate layer.

22. A method for forming a gate structure comprising:

a step for forming a gate layer over a semiconductor substrate;

a step for siliciding the gate layer;

a step for preventing siliciding at the top of the gate layer, including forming a blocking layer over the gate layer; and

a step for forming a silicide layer over the blocking layer.

23. The method of claim 22 further comprising a step for exposing sidewalls of the spacer.