Nonvolatile memory cell comprising a reduced height vertical diode
First Claim
1. A method for forming a monolithic three dimensional memory array, the method comprising:
- i) forming a first memory level, the steps for forming the first memory level comprising;
a) forming a plurality of substantially parallel, substantially coplanar first conductors above a substrate;
b) forming a plurality of substantially parallel, substantially coplanar second conductors above the first conductors;
c) forming a plurality of first vertically oriented pillars, each first pillar comprising a first junction diode and disposed between one of the first conductors and one of the second conductors,wherein the first junction diodes have a first height between about 500 angstroms and about 3000 angstroms; and
ii) monolithically forming a second memory level on the first memory level.
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Abstract
A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.
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Citations
22 Claims
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1. A method for forming a monolithic three dimensional memory array, the method comprising:
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i) forming a first memory level, the steps for forming the first memory level comprising; a) forming a plurality of substantially parallel, substantially coplanar first conductors above a substrate; b) forming a plurality of substantially parallel, substantially coplanar second conductors above the first conductors; c) forming a plurality of first vertically oriented pillars, each first pillar comprising a first junction diode and disposed between one of the first conductors and one of the second conductors, wherein the first junction diodes have a first height between about 500 angstroms and about 3000 angstroms; and ii) monolithically forming a second memory level on the first memory level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification