Integrated circuit package and method of making the same

• US 7,560,804 B1
• Filed: 01/08/2008
• Issued: 07/14/2009
• Est. Priority Date: 06/24/1998
• Status: Expired due to Fees

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Glenn, Thomas P.
• Primary Examiner(s): Parekh; Nitin
• Application Number:
  US11/970,712
• Time in Patent Office: 553 Days
• Field of Search: 257/666, 257/787, 257/784, 257/E23.046
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85439 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85447 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/85455 Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/85464 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Claims

1. An integrated circuit chip package, comprising:

a leadframe which includes;

a die pad defining opposed first and second die pad surfaces, and at least one die pad side surface extending between the first and second die pad surfaces;

a plurality of leads extending toward the die pad in spaced relation thereto, each of the leads defining opposed first and second lead surfaces and at least first and second lead side surfaces extending between the first and second lead surfaces; and

recess disposed within at least a portion of the die pad and within each of the first and second lead side surfaces of each of the leads for enhancing the connection between the die pad, the leads, and an encapsulant material applied to the die pad and the leads;

an integrated circuit die attached to the first die pad surface of the die pad and electrically connected to the first lead surface of at least some of the leads;

the encapsulant material applied to the integrated circuit die, the first die pad surface and the die pad side surface of the die pad, and to the first lead surface and the first and second lead side surfaces of each of the leads, wherein the encapsulant material does not cover the second lead surface of each of the leads.

2. The integrated circuit chip package of claim 1 wherein:

the die pad defines at least four die pad side surfaces, and a recess is disposed within each of the at least four die pad side surfaces of the die pad; and

each of the leads further defines a third lead side surface which is not covered by the encapsulant material.

3. An integrated circuit chip package, comprising:

a leadframe which includes;

a die pad defining opposed first and second die pad surfaces, and at least one die pad side surface extending between the first and second die pad surfaces;

a plurality of leads extending toward the die pad in spaced relation thereto, each of the leads defining opposed first and second lead surfaces and at least first and second lead side surfaces extending between the first and second lead surfaces; and

means disposed within the die pad side surface of the die pad and within the first and second lead side surfaces of each of the leads for enhancing the connection between the die pad, the leads, and an encapsulant material applied to the die pad and the leads;

an integrated circuit die attached to the first die pad surface of the die pad and electrically connected to the first lead surface of at least some of the leads;

the encapsulant material applied to the integrated circuit die, the first die pad surface of the die pad, the first lead surface of each of the leads, and to the means for enhancing the connection between the die pad, the leads, and the encapsulant material, wherein the encapsulant material does not cover the second lead surface of each of the leads.

4. The integrated circuit chip package of claim 3 wherein:

the die pad defines at least four die pad side surfaces, and the means for enhancing the connection between the die pad, the leads, and the encapsulant material is disposed within each of the at least four die pad side surfaces of the die pad; and

each of the leads further defines a third lead side surface which is not covered by the encapsulant material.

5. An integrated circuit chip package, comprising:

a die pad defining first and second die pad surfaces, and at least one die pad side surface extending between the first and second die pad surfaces;

a plurality of leads disposed in spaced relation to the die pad, each of the leads defining first and second lead surfaces and at least first, second and third lead side surfaces extending between the first and second lead surfaces;

means disposed within at least a portion of the die pad and within each of the first, second and third lead side surfaces of each of the leads for enhancing the connection between the die pad, the leads, and an encapsulant material applied to the die pad and the leads;

an integrated circuit die disposed upon the first die pad surface of the die pad and electrically connected to at least some of the leads;

an encapsulant material applied to at least the integrated circuit die, the first die pad surface of the die pad, the first lead surface of each of the leads, and to the means for enhancing the connection between the die pad, the leads, and the encapsulant material, the encapsulant material not covering the second lead surface of each of the leads.

6. The integrated circuit chip package of claim 5 wherein the second die pad surface of the die pad is not covered by the encapsulant material.

7. The integrated circuit chip package of claim 6 further comprising plating layers applied to the second lead surface of each of the leads and the second die pad surface of the die pad.

8. The integrated circuit chip package of claim 5 wherein the integrated circuit die is electrically connected to the first lead surface of at least some of the leads through the use of bond wires.

9. The method of claim 5 wherein the means for enhancing the connection between the die pad, the leads, and the encapsulant material is disposed within the die pad side surface of the die pad and within the lead side surface of each of the leads.

10. The integrated circuit chip package of claim 9 wherein the die pad defines at least four die pad side surfaces, and the means for enhancing the connection between the die pad, the leads, and the encapsulant material is disposed within each of the at least four die pad side surfaces of the die pad.

11. The integrated circuit chip package of claim 10 wherein the means for enhancing the connection between the die pad, the leads, and the encapsulant material comprises a recess disposed within each of the at least four die pad side surfaces of the die pad.

12. The integrated circuit chip package of claim 10 wherein the means for enhancing the connection between the die pad, the leads, and the encapsulant material comprises a notch disposed within each of the at least four die pad side surfaces of the die pad.

13. The integrated circuit chip package of claim 9 wherein each of the leads further defines a fourth lead side surface which is not covered by the encapsulant material.

14. The integrated circuit chip package of claim 13 wherein the means for enhancing the connection between the die pad, the leads, and the encapsulant material comprises a recess disposed within each of the first, second and third lead side surfaces of each of the leads.

15. The integrated circuit chip package of claim 13 wherein the means for enhancing the connection between the die pad, the leads, and the encapsulant material comprises a notch disposed within each of the first, second and third lead side surfaces of each of the leads.

16. The integrated circuit chip package of claim 9 wherein:

the die pad defines at least four die pad side surfaces, and the means for enhancing the connection between the die pad, the leads, and the encapsulant material is disposed within each of the at least four die pad side surfaces of the die pad; and

each of the leads further defines a fourth lead side surface which is not covered by the encapsulant material.

17. The integrated circuit chip package of claim 16 wherein the means for enhancing the connection between the die pad, the leads, and the encapsulant material comprises a recess disposed within each of the at least four die pad side surfaces of the die pad and within each of the first, second and third lead side surfaces of each of the leads.

18. The integrated circuit chip package of claim 16 wherein the means for enhancing the connection between the die pad, the leads, and the encapsulant material comprises a notch disposed within each of the at least four die pad side surfaces of the die pad and within each of the first, second and third lead side surfaces of each of the leads.