Programming method to reduce word line to word line breakdown for NAND flash
First Claim
Patent Images
1. A method of programming memory cells of a non-volatile NAND architecture memory array, comprising:
- applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string that is selected for programming in the NAND architecture non-volatile memory array;
selecting one or more intermediate pass voltages between the program voltage and a pass voltage;
applying each of the one or more intermediate pass voltages to a word line of a first set of one or more word lines, wherein the first set of one or more word lines are physically adjacent the selected word line;
applying the pass voltage to each word line of a second set of one or more word lines, wherein the second set of one or more word lines comprises any word line located between the first set of one or more word lines and an end of the memory string that is physically adjacent a word line of the first set of one or more word lines; and
applying a voltage selected to be between a ground and the pass voltage to each remaining unselected word line of the string that does not belong to the first set of one or more word lines or the second set of one or more word lines.
8 Assignments
0 Petitions
Accused Products
Abstract
A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell being programmed in order to reduce voltage differences between the word lines of the memory cell string or array during a programming cycle. This allows the word line to word line voltage differential to be reduced and thus decreases the likelihood of breakdown or punch through of the insulator materials placed between the adjacent word lines.
62 Citations
30 Claims
-
1. A method of programming memory cells of a non-volatile NAND architecture memory array, comprising:
-
applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string that is selected for programming in the NAND architecture non-volatile memory array; selecting one or more intermediate pass voltages between the program voltage and a pass voltage; applying each of the one or more intermediate pass voltages to a word line of a first set of one or more word lines, wherein the first set of one or more word lines are physically adjacent the selected word line; applying the pass voltage to each word line of a second set of one or more word lines, wherein the second set of one or more word lines comprises any word line located between the first set of one or more word lines and an end of the memory string that is physically adjacent a word line of the first set of one or more word lines; and applying a voltage selected to be between a ground and the pass voltage to each remaining unselected word line of the string that does not belong to the first set of one or more word lines or the second set of one or more word lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method of operating a NAND architecture memory device, comprising:
-
applying a program voltage to a selected word line coupled to a memory cell of a NAND architecture memory string that is selected for programming in a NAND architecture non-volatile memory array of the memory device; applying a first pass voltage to one or more unselected word lines of the string to operate memory cells coupled to these one or more unselected word lines as pass transistors regardless of their stored data values; applying a second pass voltage to one or more adjacent unselected word lines of the string to operate memory cells coupled to these one or more adjacent unselected word lines as pass transistors regardless of their stored data values, wherein the second pass voltage is between the first pass voltage and the program voltage and where the one or more adjacent unselected word lines are adjacent to the selected word line; and applying a voltage selected to be between a ground and the first pass voltage to one or more unselected word lines located between an end of the memory string and a word line receiving the first pass voltage, wherein that word line receiving the first pass voltage is located between the end of the memory string and the selected word line. - View Dependent Claims (12, 13, 14, 15, 16)
-
-
17. A non-volatile NAND architecture memory device comprising:
-
a NAND architecture non-volatile memory array having a plurality of memory blocks; and a control circuit, wherein the control circuit is adapted to program memory cells in a selected memory block of the non-volatile memory array by, applying a program voltage to a selected word line coupled to a memory cell of a NAND architecture memory string that is selected for programming in a NAND architecture non-volatile memory array of the memory device; applying a first pass voltage to one or more unselected word lines of the string to operate memory cells coupled to these one or more unselected word lines as pass transistors regardless of their stored data values; applying a second pass voltage to one or more adjacent unselected word lines of the string to operate memory cells coupled to these one or more adjacent unselected word lines as pass transistors regardless of their stored data values, wherein the second pass voltage is between the first pass voltage and the program voltage and where the one or more adjacent unselected word lines are adjacent to the selected word line; and applying a voltage selected to be between a ground and the first pass voltage to one or more unselected word lines located between an end of the memory string and a word line receiving the first pass voltage, wherein that word line receiving the first pass voltage is located between the end of the memory string and the selected word line. - View Dependent Claims (18, 19, 20, 21, 22)
-
-
23. A system comprising:
a host coupled to a non-volatile memory device, wherein the non-volatile memory device comprises; a NAND architecture non-volatile memory array having a plurality of blocks; wherein the system is adapted to program memory cells in a selected block of the non-volatile memory array by; selecting one or more memory cells in one or more NAND architecture memory cell strings for programming in the selected block of non-volatile memory cells, where the one or more selected memory cells in each of the one or more memory cell strings is coupled to a selected word line, applying a program voltage to the word line coupled to the one or more selected memory cells, applying a first pass voltage to one or more unselected word lines of the one or more memory cell strings to operate memory cells coupled to these one or more unselected word lines as pass transistors regardless of their stored data values; applying a second pass voltage to one or more adjacent unselected word lines of the one or more memory cell strings to operate memory cells coupled to these one or more adjacent unselected word lines as pass transistors regardless of their stored data values, wherein the second pass voltage is selected to be between the first pass voltage and the program voltage and where the one or more adjacent unselected word lines are physically adjacent to the selected word line; and applying a voltage selected to be between a ground and the first pass voltage to one or more unselected word lines located between an end of the memory string and a word line receiving the first pass voltage, wherein that word line receiving the first pass voltage is located between the end of the memory string and the selected word line. - View Dependent Claims (24, 25, 26, 27)
-
28. A memory module, comprising:
-
a plurality of contacts; and two or more memory devices, each having access lines selectively coupled to the plurality of contacts; wherein at least one of the memory device comprises; a NAND architecture non-volatile memory array having a plurality of memory blocks; wherein the memory module is adapted to program memory cells in a selected block of the non-volatile memory array by; applying a program voltage to a selected word line coupled to a memory cell of a NAND architecture memory string that is selected for programming in the memory array of the memory device; applying a first pass voltage to one or more unselected word lines of the string to operate memory cells coupled to these one or more unselected word lines as pass transistors regardless of their stored data values; applying a second pass voltage to one or more adjacent unselected word lines of the string to operate memory cells coupled to these one or more adjacent unselected word lines as pass transistors regardless of their stored data values, wherein the second pass voltage is between the first pass voltage and the program voltage and where the one or more adjacent unselected word lines are physically adjacent to the selected word line; and applying a voltage selected to be between a ground and the first pass voltage to one or more unselected word lines located between an end of the memory string and a word line receiving the first pass voltage, wherein that word line receiving the first pass voltage is located between the end of the memory string and the selected word line. - View Dependent Claims (29)
-
-
30. A memory module, comprising:
-
a housing having a plurality of contacts; and one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts; wherein the memory module is adapted to program memory cells in a selected block of at least one of the memory devices by; applying a program voltage to a selected word line coupled to one or more memory cells of one or more NAND architecture memory cell strings that are selected for programming in the selected block of the memory device; applying a first pass voltage to one or more unselected word lines of the string one or more memory cell strings to operate memory cells coupled to these one or more unselected word lines as pass transistors regardless of their stored data values; applying a second pass voltage to one or more second unselected word lines of the one or more memory cell strings to operate memory cells coupled to these one or more second unselected word lines as pass transistors regardless of their stored data values, wherein the one or more second unselected word lines are adjacent to the selected word line and the second pass voltage is between the first pass voltage and the program voltage; and applying a voltage selected to be between a ground and the first pass voltage to one or more unselected word lines located between an end of the memory string and a word line receiving the first pass voltage.
-
Specification